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ADP7156 Arkusz danych(PDF) 7 Page - Analog Devices |
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ADP7156 Arkusz danych(HTML) 7 Page - Analog Devices |
7 / 24 page ADP7157 Data Sheet Rev. A | Page 6 of 23 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 4 BYP 5 EN 2 VOUT 3 VOUT_SENSE 7 REF 6 REF_SENSE 9 8 NOTES 1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF THE PACKAGE. THE EXPOSED PAD ENHANCES THERMAL PERFORMANCE, AND IT IS ELECTRICALLY CONNECTED TO GROUND INSIDE THE PACKAGE. CONNECT THE EP TO THE GROUND PLANE ON THE BOARD TO ENSURE PROPER OPERATION. 1 VOUT 10 VIN VREG VIN ADP7157 TOP VIEW (Not to Scale) Figure 3. 10-Lead LFCSP Pin Configuration VOUT 1 VOUT_SENSE 2 BYP 3 EN 4 VIN 8 VREG 7 REF 6 REF_SENSE 5 NOTES 1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF THE PACKAGE. THE EXPOSED PAD ENHANCES THERMAL PERFORMANCE, AND IT IS ELECTRICALLY CONNECTED TO GROUND INSIDE THE PACKAGE. CONNECT THE EP TO THE GROUND PLANE ON THE BOARD TO ENSURE PROPER OPERATION. ADP7157 TOP VIEW (Not to Scale) Figure 4. 8-Lead SOIC Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description LFCSP SOIC 1, 2 1 VOUT Regulated Output Voltage. Bypass VOUT to ground with a 10 μF or greater capacitor. 3 2 VOUT_SENSE Output Sense. VOUT_SENSE is internally connected to VOUT with a 10 Ω resistor. Connect VOUT_SENSE as close to the load as possible. 4 3 BYP Low Noise Bypass Capacitor. Connect a 1 μF or greater capacitor from the BYP pin to ground to reduce noise. Do not connect a load to this pin. 5 4 EN Enable. Drive EN high to turn on the regulator, and drive EN low to turn off the regulator. For automatic startup, connect EN to VIN. 6 5 REF_SENSE Reference Sense. This pin sets the output voltage with an external resistor divider. VOUT = VREF × (R1 + R2)/R2, where VREF = 1.2 V. Connect REF_SENSE to the REF pin. Do not connect REF_SENSE to VOUT or ground. 7 6 REF Low Noise Reference Voltage Output. Bypass REF to ground with a 1 μF or greater capacitor. Short REF_SENSE to REF for fixed output voltages. Do not connect a load to this pin. 8 7 VREG Regulated Input Supply Voltage to the LDO Amplifier. Bypass VREG to ground with a 1 μF or greater capacitor. 9, 10 8 VIN Regulator Input Supply Voltage. Bypass VIN to ground with a 10 μF or greater capacitor. EP Exposed Pad. The exposed pad is located on the bottom of the package. The exposed pad enhances thermal performance, and it is electrically connected to ground inside the package. Connect the exposed pad to the ground plane on the board to ensure proper operation. |
Podobny numer części - ADP7156 |
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Podobny opis - ADP7156 |
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