MC100LVEP14

http://onsemi.com

2

Figure 1. 20−Lead Pinout (Top View) and Logic Diagram

to Power Supply to guarantee proper operation.

Q2

Q1

Q3

Q1

17

18

16

15

14

13

12

4

3

56

78

9

11

10

CLK1

CLK0

CLK0

Q0

19

20

2

1

EN

Q2

Q0

Q3

Q4

Q4

CLK1

10

D

Q

CLK_SEL

Table 1. PIN DESCRIPTION

Pin

Type

Function

CLK0*,

CLK0**

LVECL/LVPECL/

HSTL

ECL/PECL/HSTL CLK Input

CLK1*,

CLK1**

LVECL/LVPECL/

HSTL

ECL/PECL/HSTL CLK Input

Q0:4, Q0:4

LVECL/LVPECL

ECL/PECL Outputs

CLK_SEL*

LVECL/LVPECL

ECL/PECL Active Clock Se-

lect Input

EN*

LVECL/LVPECL

ECL Sync Enable

LVECL/LVPECL

Reference Voltage Output

Positive Supply

Negative Supply

* Pins will default low when left open.

Table 2. FUNCTION TABLE

CLK0

CLK1

CLK_SEL

EN

Q

L

H

X

X

X

X

X

L

H

X

L

L

H

H

X

L

L

L

L

H

L

H

L

H

L*

*On next negative transition of CLK0 or CLK1

Table 3. ATTRIBUTES

Characteristics

Value

Internal Input Pulldown Resistor

75 k

W

Internal Input Pullup Resistor

37.5 k

W

ESD Protection

Human Body Model

Machine Model

Charged Device Model

> 2 kV

> 100 V

> 2 kV

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

Pb Pkg

Pb−Free Pkg

TSSOP−20

Level 1

Level 1

Flammability Rating

Oxygen Index: 28 to 34

UL 94 V−0 @ 0.125 in

Transistor Count

357 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.