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MTV018 Arkusz danych(PDF) 3 Page - List of Unclassifed Manufacturers

Numer części MTV018
Szczegółowy opis  Super On-Screen-Display
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Producent  ETC [List of Unclassifed Manufacturers]
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MTV018 Arkusz danych(HTML) 3 Page - List of Unclassifed Manufacturers

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MTV018 Revision 4.0 10/21/1999
MTV018
MYSON
TECHNOLOGY
3.0 FUNCTIONAL DESCRIPTIONS
3.1 SERIAL DATA INTERFACE
The serial data interface receives data transmitted from an external controller. And there are 2 types of bus
can be accessed through the serial data interface, one is SPI bus and other is I2C bus.
3.1.1 SPI bus
While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. And a valid transmission
should be starting from pulling SSB to "low" level, enabling MTV018 to receiving mode, and retain "low" level
until the last cycle for a complete data packet transfer. The protocol is shown in Figure 1.
PWM2
O
-
-
11
Open-Drain PWM D/A converter 2. The output pulse width is pro-
grammable by the register of Row 15, Column 21.
PWM3
O
-
-
12
Open-Drain PWM D/A converter 3. The output pulse width is pro-
grammable by the register of Row 15, Column 22.
PWM4
O
-
-
13
Open-Drain PWM D/A converter 4. The output pulse width is pro-
grammable by the register of Row 15, Column 23.
PWM5
O
-
-
14
Open-Drain PWM D/A converter 5. The output pulse width is pro-
grammable by the register of Row 15, Column 24.
PWM6
O
-
11
15
Open-Drain PWM D/A converter 6. The output pulse width is pro-
grammable by the register of Row 15, Column 25.
PWM7
O
-
12
16
Open-Drain PWM D/A converter 7. The output pulse width is pro-
grammable by the register of Row 15, Column 26.
VDD
-
9
13
17
Digital power supply. Positive 5 V DC supply for internal digital cir-
cuitry and a 0.1uF decoupling capacitor should be connected across
to VDD and VSS.
VFLB
I
10
14
18
Vertical input. This pin is used to input the vertical synchronizing sig-
nal. It is leading triggered and has an internal pull-up resistor.
HTONE /
PWMCK
O
11
15
19
Half tone output / PWM clock output. This is a multiplexed pin
selected by PWMCK bit. This pin can be a PWM clock or used to
attenuate R, G, B gain of VGA for the transparent windowing effect.
FBKG
O
12
16
20
Fast Blanking output. It is used to cut off external R, G, B signals of
VGA while this chip is displaying characters or windows.
BOUT
O
13
17
21
Blue color output. It is a blue color video signal output.
GOUT
O
14
18
22
Green color output. It is a green color video signal output.
ROUT
O
15
19
23
Red color output. It is a red color video signal output.
VSS
-
16
20
24
Digital ground. This ground pin is used to internal digital circuitry.
Name
I/O
Pin No.
Descriptions
N
N20
N24


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