7/13

BU2092F BU2092FV

TSZ02201-0RHR1GZ00130-1-2

© 2013 ROHM Co., Ltd. All rights reserved.

18.Sep.2015 Rev.002

www.rohm.com

TSZ22111・15・001

Timing Chart

1.

After the power is turned on and the voltage is stabilized, LCK should be activated, after clocking 12 data bits

into the DATA terminal.

2.

Qx parallel output data of the shift register is set after the 12

3.

Since the LCK is a label latch, data is retained in the “L” section and renewed in the “H” section of the LCK.

4.

Data retained in the internal latch circuit is output when the OE is in the “L” section.

［

Truth Table］

Input

Function

CLOCK

DATA

LCK

OE

×

×

×

H

Output (Q0 to Q11) Disable

×

×

×

L

Output (Q0 to Q11) Enable

L

×

×

Store “L” in the first stage data of shift register, the previous stage data in the

others. (The conditions of storage register and output have no change.)

H

×

×

Store “H” in the first stage data of shift register, the previous stage data in the

others. (The conditions of storage register and output have no change.)

×

×

×

The data of shift register has no change.

×

×

×

The data of shift register is transferred to the storage register.

×

×

×

The data of storage register has no change.

I/O Equivalence Circuits

Q0 to Q11

CLOCK

LCK

OE

Qx

Previous DATA

DATA11～0

“H”

DATA

DATA11

DATA10 DATA9

DATA1

DATA0

Figure 6 . Timing Chart

(Note3) Diagram shows a status where a pull-up resistor is connected to output.

VSS

Qx

DATA

CLOCK

LCK

OE

VSS

VSS

VDD

VDD

DATA,CLOCK,LCK,OE