UC1844A-SP datasheet(11/31 Pages) TI1

Numer części	UC1844A-SP

Szczegółowy opis	QML Class V, Current-Mode PWM Controller

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Producent	TI1 [Texas Instruments]

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UC1842A-SP, UC1843A-SP, UC1844A-SP

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SLUS872D – JANUARY 2009 – REVISED MAY 2015

Feature Description (continued)

Figure 3. Inductor Looks Like a Current Source to Small Signals

A. Direct duty cycle control

B. Current mode control

Figure 4. Required Error Amplifier Compensation for Continuous Inductor Current Designs

9.3.1 UVLO

The UVLO circuit ensures that VCC is adequate to make the UC184xA fully operational before enabling the

output stage. Figure 5 shows that the UVLO turn-on and turn-off thresholds are fixed internally at 16 V and 10 V,

respectively. The 6-V hysteresis prevents VCC oscillations during power sequencing. Figure 6 shows supply

current requirements. Start-up current is <1 mA for efficient bootstrapping from the rectified input of an off-line

converter, as shown in Figure 7. During normal circuit operation, VCC is developed from auxiliary winding, WAux,

with D1 and CIN. However, at start-up, CIN must be charged to 16 V through RIN. With a start-up current of 1 mA,

RIN can be as large as 100 kΩ and still charge CIN when VAc = 90-V RMS (low line). Power dissipation in RIN

would then be less than 350 mW even under high line (VAc = 130-V RMS) conditions.

During UVLO, the output driver is in a low state. While it does not exhibit the same saturation characteristics as

normal operation, it can easily sink 1 mA, enough to ensure the MOSFET is held off.

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