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LM2612ABP Arkusz danych(PDF) 4 Page - National Semiconductor (TI) |
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LM2612ABP Arkusz danych(HTML) 4 Page - National Semiconductor (TI) |
4 / 19 page Electrical Characteristics (Continued) Specifications with standard typeface are for T A =TJ = 25˚C, and those in bold face type apply over the full Operating Tem- perature Range (T A =TJ = −25˚C to +85˚C). Unless otherwise specified, PVIN = VDD = EN = SYNC = 3.6V, VID0 = VID1 = 0V. Symbol Parameter Conditions Min Typ Max Units I VID VID1, VID0 Pull Down Current VID1, VID0 = 3.6V 1.8 µA f sync SYNC/MODE Clock Frequency Range (Note 10) 500 1000 kHz F OSC Internal Oscillator Frequency LM2612ABP, PWM Mode (SYNC = VIN) 468 600 732 kHz LM2612BBP, PWM Mode (SYNC = VIN) 450 600 750 T min Minimum ON-Time of P FET Switch in PWM Mode 200 ns Load Transient Response in PWM Mode Circuit of Figure 1 I OUT = 20mA to 200mA Step ±25 mV Line Transient Response in PFM Mode Circuit of Figure 1 V IN = 3.0V to 3.6V Step t r =tp =10 µs ±3mV Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended to be functional, but parameter specifications may not be guaranteed. For guaranteed specifications and associated test conditions, see the Min and Max limits and Conditions in the Electrical Characteristics table. Electrical Characteristics table limits are guaranteed by production testing, design or correlation using standard Statistical Quality Control methods. Typical (Typ) specifications are mean or average values from characterization at 25C and are not guaranteed. Note 2: In PWM mode, Thermal shutdown will occur if the junction temperature exceeds the 150˚C maximum junction temperature of the device. Note 3: Thermal resistance specified with 2 layer PCB(0.5/0.5 oz. cu). Note 4: Thermal resistance specified with 3 layer PCB (2/1/1 oz. cu) and 12 vias 0.33mm diameter (see Application Note AN-1187). Note 5: The LM2612 is designed for cell phone applications where turn-on after power-up is controlled by the system processor and internal UVLO (Under Voltage LockOut) circuitry is unecessary. The LM2612 has no UVLO circuitry and should be kept in shutdown by holding the EN pin low until the input voltage exceeds 2.8V. Although the LM2612 exhibited safe behavior during pre-production evaluation while enabled at low input voltages, this is not guaranteed. Note 6: The feedback voltage is trimmed at the 1.5V output setting. The other output voltages result from the pin selection of the internal DAC’s divider ratios. The precision for the feedback voltages is ±2%, except for the 1.05V setting, which is 5%. Contact the Portable Power Applications group at National Semiconductor, if trimming at other voltages is desired. Note 7: : The hysteresis voltage is the minimum voltage swing on FB that causes the internal feedback and control circuitry to turn the internal PFET switch on and then off, during PFM mode. Note 8: Current limit is built-in, fixed, and not adjustable. If the current limit is reached while the output is pulled below about 0.7V, the internal PFET switch turns off for 2.5 µs to allow the inductor current to diminish. Note 9: EN is a CMOS Schmitt trigger digital input with logic thresholds that scale with the supply voltage at the VDD pin. The nominal logic thresholds are approximately 0.71VDD and 0.55VDD for the high and low thresholds respectively. Note 10: SYNC driven with an external clock switching between VIN and GND. When an external clock is present at SYNC, the IC is forced to PWM mode at the external clock frequency. The LM2612 synchronizes to the rising edge of the external clock. www.national.com 4 |
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