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LM2612ABPX Arkusz danych(PDF) 2 Page - National Semiconductor (TI) |
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LM2612ABPX Arkusz danych(HTML) 2 Page - National Semiconductor (TI) |
2 / 19 page Connection Diagrams micro SMD package 20007104 TOP VIEW 20007105 BOTTOM VIEW Ordering Information Order Number Package Type NSC Package Drawing Supplied As 10-Pin micro SMD LM2612ABP 10-bump Wafer Level Chip Scale (micro SMD) BPA10VWB 250 Units, Tape and Reel LM2612BBP 250 Units, Tape and Reel LM2612ABPX 3000 Units, Tape and Reel LM2612BBPX 3000 Units, Tape and Reel Pin Description Pin Number(*) Pin Name Function A1 FB Feedback Analog Input. Connect to the output at the output filter capacitor (Figure 1) B1 VID1 Output Voltage Control Inputs. Set the output voltage using these digital inputs (see Table 1). The output defaults to 1.5V if these pins are unconnected. C1 VID0 D1 SYNC/MODE Synchronization Input. Use this digital input for frequency selection or modulation control. Set: SYNC/MODE = high for low-noise 600kHz PWM mode SYNC/MODE = low for low-current PFM mode SYNC/MODE = a 500kHz - 1MHz external clock for synchronization to an external clock in PWM mode. See Synchronization and Operating Modes in the Device Information section. D2 EN Enable Input. Set this CMOS Schmitt trigger digital input high to VDD for normal operation. For shutdown, set low to SGND. Set EN low during power-up and other low supply voltage conditions. (See Shutdown Mode in the Device Information section.) D3 PGND Power Ground C3 SW Switching Node connection to the internal PFET switch and NFET synchronous rectifier. Connect to an inductor with a saturation current rating that exceeds the 850mA max Switch Peak Current Limit specification of the LM2612 ( Figure 1) B3 PVIN Power Supply Input to the internal PFET switch. Connect to the input filter capacitor ( Figure 1). A3 VDD Analog Supply Input. If board layout is not optimum, an optional 0.1µF ceramic capacitor is suggested ( Figure 1) A2 SGND Analog and Control Ground (*) note the pin numbering scheme for the MicroSMD package was revised in April, 2002 to comform to JEDEC standard. Only the pin numbers were revised. No changes to the physical location of the inputs/outputs were made. For reference purpose, the obsolete numbering has FB as pin 1, VID1 as pin 2, VID0 as pin3, SYNC as pin 4, EN as pin 5, PGND as pin 6, SW as pin 7, PVIN as pin 8, VDD as pin 9 and SGND as pin 10. www.national.com 2 |
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