Zakładka z wyszukiwarką danych komponentów
  Polish  ▼
ALLDATASHEET.PL

X  

CS8402A Arkusz danych(PDF) 10 Page - List of Unclassifed Manufacturers

Numer części CS8402A
Szczegółowy opis  Digital Audio Interface Transmitter
Download  34 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Producent  ETC [List of Unclassifed Manufacturers]
Strona internetowa  
Logo ETC - List of Unclassifed Manufacturers

CS8402A Arkusz danych(HTML) 10 Page - List of Unclassifed Manufacturers

Back Button CS8402A Datasheet HTML 6Page - List of Unclassifed Manufacturers CS8402A Datasheet HTML 7Page - List of Unclassifed Manufacturers CS8402A Datasheet HTML 8Page - List of Unclassifed Manufacturers CS8402A Datasheet HTML 9Page - List of Unclassifed Manufacturers CS8402A Datasheet HTML 10Page - List of Unclassifed Manufacturers CS8402A Datasheet HTML 11Page - List of Unclassifed Manufacturers CS8402A Datasheet HTML 12Page - List of Unclassifed Manufacturers CS8402A Datasheet HTML 13Page - List of Unclassifed Manufacturers CS8402A Datasheet HTML 14Page - List of Unclassifed Manufacturers Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 34 page
background image
channel status data cyclic redundancy check
characters are generated independently for chan-
nels A and B and are transmitted at the end of the
channel status block. When MUTE (bit 1) is low,
the transmitted audio data is forced to zero. Both
RST and MUTE are set to zero upon power up.
When RST is low, the differential line drivers are
set to ground and the block counters are reset to the
beginning of the first block. In order to properly
synchronize the rest of the CS8401A to the audio
serial port, the transmit timing counters, which in-
clude the flags in the status register, are not enabled
after RST is set high until eight and one half SCK
periods after the active edge (first edge after reset is
exited) of FSYNC.
When FSYNC is configured as a left/right signal
(FSF1 = 1), the counters and flags are not en-
abled until the right sample is being entered
(during which the previous left sample is being
transmitted). This guarantees that channel A is
left and Channel B is right as per the digital
audio interface specs.
Control register 3 contains format information for
the serial audio input channel. The MSB is unused
and the next three bits, SDF2-SDF0, select the for-
mat for the serial input data with respect to
FSYNC. There are five valid combinations of these
bits as shown in Figure 10. The next two bits,
FSF1 and FSF0, select the format of FSYNC. Two
of the formats delineate each channel’s data and
do not indicate the particular channel. The other
two formats also indicate the specific channel.
The formats are shown in Figure 10. Bit 1,
MSTR, determines whether FSYNC and SCK
are inputs, MSTR low, or outputs, MSTR high.
Bit 0, serial clock edge select, SCED, selects the
edge that audio data gets latched on. When
SCED is low, the falling edge of SCK latches
data in the chip and when SCED is high, the ris-
ing edge is used.
The multitude of combinations allow for a zero
glue logic interface to almost all DSP’s, encoder
chips, and standard serial data formats.
Serial Port
The serial port is used to enter audio data and
consists of three pins: SCK, SDATA, and
FSYNC. The serial port is double buffered with
SCK clocking in the data from SDATA, and
FSYNC delineating audio samples and may de-
fine the particular channel, left or right.
Control register 3, shown in Figure 9, configures
the serial port. All the various formats are illus-
trated in Figure 10. When FSF1 is low, FSYNC
only delineates audio samples. When FSF1 is
high, it delineates audio samples and specifies
the channel. When FSF1 is low and the port is a
master (MSTR = 1), FSYNC is a square wave
output. When FSF1 is low and the port is a slave
(input), FSYNC can be a square wave or a pulse
provided the active edge, as defined in Fig-
ure 10, is properly positioned with respect to
SDATA.
Bits 4, 5, and 6, SDF0-SDF2, define the format
of SDATA and is also described in Figure 10.
The five allowable formats are MSB first, MSB
last, 16-bit LSB last, 18-bit LSB last, and 20-bit
LSB last. The MSB first and MSB last formats
accept any word length from 16 to 24 bits. The
word length is controlled by providing trailing
zeros in MSB first mode and leading zeros in
0
1
2
3
4
5
6
7
X:03
SCED
MSTR
FSF0
SDF2
SDF0
FSF1
When clear, falling edge of SCK latches data.
SDF1
FSF1: with FSF0, select FSYNC format.
SDF0: with SDF1 & SDF2, select serial data format.
FSF0: with FSF1, select FSYNC format.
SDF2: with SDF0 & SDF1, select serial data format.
SDF1: with SDF0 & SDF2, select serial data format.
MSTR: When set, SCK and FSYNC are outputs.
SCED: When set, rising edge of SCK latches data.
Figure 9. Control Register 3
CS8401A
10
DS60F1


Podobny numer części - CS8402A

ProducentNumer częściArkusz danychSzczegółowy opis
logo
Pulse A Technitrol Comp...
CS8402 PULSE-CS8402 Datasheet
81Kb / 2P
   TRANSFORMERS FOR DIGITAL AUDIO DATA TRANSMISSION
More results

Podobny opis - CS8402A

ProducentNumer częściArkusz danychSzczegółowy opis
logo
List of Unclassifed Man...
YM3437C ETC-YM3437C Datasheet
969Kb / 11P
   DIGITAL AUDIO INTERFACE TRANSMITTER
logo
STMicroelectronics
STA020 STMICROELECTRONICS-STA020_10 Datasheet
214Kb / 14P
   96kHz DIGITAL AUDIO INTERFACE TRANSMITTER
April 2010
STA020D STMICROELECTRONICS-STA020D_02 Datasheet
130Kb / 11P
   96kHz DIGITAL AUDIO INTERFACE TRANSMITTER
STA020 STMICROELECTRONICS-STA020 Datasheet
94Kb / 12P
   96kHz DIGITAL AUDIO INTERFACE TRANSMITTER
logo
Cirrus Logic
CS8406 CIRRUS-CS8406 Datasheet
629Kb / 43P
   192 KHZ DIGITAL AUDIO INTERFACE TRANSMITTER
CS8406 CIRRUS-CS8406_12 Datasheet
406Kb / 39P
   192 kHz Digital Audio Interface Transmitter
CS8405A CIRRUS-CS8405A_04 Datasheet
630Kb / 37P
   96 kHz Digital Audio Interface Transmitter
CS8406 CIRRUS-CS8406_09 Datasheet
306Kb / 42P
   192 kHz Digital Audio Interface Transmitter
logo
ADTech
ADT5116TA ADTECH-ADT5116TA Datasheet
84Kb / 2P
   transmitter IC for digital audio interface
logo
Cirrus Logic
CS8405A CIRRUS-CS8405A Datasheet
739Kb / 36P
   96 KHZ DIGITAL AUDIO INTERFACE TRANSMITTER
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34


Arkusz danych Pobierz

Go To PDF Page


Link URL




Polityka prywatności
ALLDATASHEET.PL
Czy Alldatasheet okazała się pomocna?  [ DONATE ] 

O Alldatasheet   |   Reklama   |   Kontakt   |   Polityka prywatności   |   Linki   |   Lista producentów
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com