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MC14018BDG Arkusz danych(PDF) 1 Page - ON Semiconductor

Numer części MC14018BDG
Szczegółowy opis  Presettable Divide-By-N Counter
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MC14018BDG Arkusz danych(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 8
1
Publication Order Number:
MC14018B/D
MC14018B
Presettable Divide-By-N
Counter
The MC14018B contains five Johnson counter stages which are
asynchronously presettable and resettable. The counters are
synchronous, and increment on the positive going edge of the clock.
Presetting is accomplished by a logic 1 on the preset enable input.
Data on the Jam inputs will then be transferred to their respective Q
outputs (inverted). A logic 1 on the reset input will cause all Q outputs
to go to a logic 1 state.
Division by any number from 2 to 10 can be accomplished by
connecting appropriate Q outputs to the data input, as shown in the
Function Selection table. Anti−lock gating is included in the
MC14018B to assure proper counting sequence.
Features
Fully Static Operation
Schmitt Trigger on Clock Input
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
Pin−for−Pin Replacement for CD4018B
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
This Device is Pb−Free and is RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
−0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
−0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
−55 to +125
°C
Tstg
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature
(8−Second Soldering)
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/
_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
MARKING DIAGRAM
SOIC−16
D SUFFIX
CASE 751B
14018BG
AWLYWW
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W
= Work Week
G
= Pb−Free Indicator
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
1
16
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
JAM 5
Q5
C
R
VDD
JAM 4
PE
Q4
Q2
JAM 2
JAM 1
Din
VSS
JAM 3
Q3
Q1
FUNCTIONAL TRUTH TABLE
Preset
Jam
Clock
Reset
Enable
Input
Qn
00
X
Qn
00
X
Dn*
X0
1
0
1
X0
1
1
0
X1
X
X
1
*Dn is the Data input for that stage. Stage 1
has Data brought out to Pin 1.


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