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MC14049UB Arkusz danych(PDF) 1 Page - ON Semiconductor |
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MC14049UB Arkusz danych(HTML) 1 Page - ON Semiconductor |
1 / 7 page © Semiconductor Components Industries, LLC, 2014 May, 2014 − Rev. 9 1 Publication Order Number: MC14049UB/D MC14049UB Hex Buffers The MC14049UB hex inverter/buffer is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. This complementary MOS device finds primary use where low power dissipation and/or high noise immunity is desired. This device provides logic−level conversion using only one supply voltage, VDD. The input−signal high level (VIH) can exceed the VDD supply voltage for logic−level conversions. Two TTL/DTL Loads can be driven when the device is used as CMOS−to−TTL/DTL converters (VDD = 5.0 V, VOL v 0.4 V, IOL ≥ 3.2 mA). Note that pins 13 and 16 are not connected internally on this device; consequently connections to these terminals will not affect circuit operation. Features • High Source and Sink Currents • High−to−Low Level Converter • Supply Voltage Range = 3.0 V to 18 V • Meets JEDEC UB Specifications • VIN can exceed VDD • Improved ESD Protection on All Inputs • These Devices are Pb−Free and are RoHS Compliant • NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol Parameter Value Unit VDD DC Supply Voltage Range − 0.5 to +18.0 V Vin Input Voltage Range (DC or Transient) − 0.5 to +18.0 V Vout Output Voltage Range (DC or Transient) −0.5 to VDD +0.5 V Iin Input Current (DC or Transient) per Pin ±10 mA Iout Output Current (DC or Transient) per Pin +45 mA PD Power Dissipation, per Package (Note 1) Plastic SOIC 825 740 mW TA Ambient Temperature Range − 55 to +125 °C Tstg Storage Temperature Range − 65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Temperature Derating: All Packages: See Figure 4. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields referenced to the VSS pin, only. Extra precautions must be taken to avoid applications of any voltage higher than the maximum rated voltages to this high−impedance circuit. For proper operation, the ranges VSS v Vin v 18 V and VSS v Vout v VDD are recommended. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. ORDERING INFORMATION http://onsemi.com MARKING DIAGRAMS SOIC−16 D SUFFIX CASE 751B TSSOP−16 DT SUFFIX CASE 948F 14049UG AWLYWW SOEIAJ−16 F SUFFIX CASE 966 MC14049UB ALYWG 1 16 1 16 14 049UB ALYW G G 1 16 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) |
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