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AD9525 Arkusz danych(PDF) 11 Page - Analog Devices |
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AD9525 Arkusz danych(HTML) 11 Page - Analog Devices |
11 / 48 page Data Sheet AD9525 Rev. A | Page 11 of 48 SERIAL CONTROL PORT Table 19. Parameter Min Typ Max Unit Test Conditions/Comments CS (INPUT) CS has an internal 30 kΩ pull-up resistor Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 2.5 µA Input Logic 0 Current −112 µA The minus sign indicates that current is flowing out of the AD9525, which is due to the internal pull-up resistor Input Capacitance 2 pF SCLK (INPUT) SCLK has an internal 30 kΩ pull-down resistor Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 112 µA Input Logic 0 Current 1 µA Input Capacitance 2 pF SDIO (WHEN INPUT) Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 10 nA Input Logic 0 Current 20 nA Input Capacitance 2 pF SDIO, SDO (OUTPUTS) 1 mA load current Output Logic 1 Voltage 2.7 V Output Logic 0 Voltage 0.4 V TIMING Clock Rate (SCLK, 1/tSCLK) 31 MHz Pulse Width High, tHIGH 16 ns Pulse Width Low, tLOW 16 ns SDIO to SCLK Setup, tDS 2 ns SCLK to SDIO Hold, tDH 1.1 ns SCLK to Valid SDIO and SDO, tDV 12 ns CS to SCLK Setup and Hold, tS, tH 2 ns CS Minimum Pulse Width High, tPWH 3.6 ns |
Podobny numer części - AD9525_13 |
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Podobny opis - AD9525_13 |
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