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BD3460FS Arkusz danych(PDF) 10 Page - Rohm |
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BD3460FS Arkusz danych(HTML) 10 Page - Rohm |
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10 / 30 page  BD3460FS 10/26 TSZ02201-0C2C0E100350-1-2 © 2015 ROHM Co., Ltd. All rights reserved. 16.Dec.2015 Rev.001 www.rohm.com TSZ22111・15・001 Timing Chart CONTROL SIGNAL SPECIFICATIONS (1) Electrical Specifications and Timing for Bus Lines and I/O Stages Figure 16. I2C-bus Signal Timing Diagram Table 1 Characteristics of the SDA and SCL bus lines for I2C-bus devices (Unless specified, Ta=25°C, VCC=8.5V) Parameter Symbol Fast-mode I2C-bus Unit Min Max 1 SCL clock frequency fSCL 0 400 kHz 2 Bus free time between a STOP and START condition tBUF 1.3 － μS 3 Hold time (repeated) START condition. After this period, the first clock pulse is generated tHD;STA 0.6 － μS 4 LOW period of the SCL clock tLOW 1.3 － μS 5 HIGH period of the SCL clock tHIGH 0.6 － μS 6 Set-up time for a repeated START condition tSU;STA 0.6 － μS 7 Data hold time tHD;DAT 0 (Note) － μS 8 Data set-up time tSU;DAT 100 － ns 9 Set-up time for STOP condition tSU;STO 0.6 － μS All values referred to VIH Min and VIL Max Levels (see Table 2). (Note) To avoid sending right after the fall-edge of SCL (VIHmin of the SCL signal), the transmitter sets a holding time of 300ns or more for the SDA signal. About 7(tHD;DAT), 8(tSU;DAT), make it the setup which a margin is fully in . Table 2 Characteristics of the SDA and SCL I/O stages for I2C-bus devices Parameter Symbol Fast-mode devices Unit Min Max 10 LOW level input voltage VIL -0.5 +1 V 11 HIGH level input voltage VIH 2.3 － V 12 Pulse width of spikes which must be suppressed by the input filter. tSP 0 50 ns 13 LOW level output voltage (open drain or open collector) at 3mA sink current VOL1 0 0.4 V 14 Input current of each I/O pin with an input voltage between 0.4V and 4.5V II -10 +10 μA SDA S SCL tLOW tR tHD;DAT P tHD;STA tHIGH tBUF tF tSU;DAT tSU;STAT tSU;STOT tSP tHD;STAT Sr P Figure 17. I2C Command Data Transmission Timing Diagram ｔBUF ：4us ｔHD;STA ：2us ｔHD;DAT ：1us ｔLOW ：3us ｔHIGH ：1us ｔSU;DAT ：1us ｔSU;STO ：2us SCL clock frequency：250kHz SCL SDA tHD;STA :2µs tHD;DAT :1µs tSU;DAT :1µs tSU;STO :2µs tLOW :3µs tBUF :4µs tHIGH :1µs SDA SCL SCL clock frequency : 250kHz |
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