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BD34704KS2 Arkusz danych(PDF) 9 Page - Rohm |
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BD34704KS2 Arkusz danych(HTML) 9 Page - Rohm |
9 / 40 page 9/36 Datasheet Datasheet BD34704KS2 TSZ02201-0C2C0E100210-1-2 © 2015 ROHM Co., Ltd. All rights reserved. 2015.2.25 Rev.002 www.rohm.com TSZ22111・15・001 Specifications for Control Signal (4) Timing of control signal Data is read at the rising edge of clock. Latch is read at the falling edge of clock. Data on the latest 16bit is taken inside the IC. Ensure to set DA and CL to LOW after Latch. 1byte=16bit Item Symbol Limit Unit Min Typ Max Clock width twc 1.0 - - µsec Data width twd 1.0 - - µsec Latch width twl 1.0 - - µsec Low hold width twh 1.0 - - µsec Data setup time (DATA→CLK) tsd 0.5 - - µsec Data hold time (CLK→DATA) thd 0.5 - - µsec Latch setup time (CLK→LATCH) tsl 0.5 - - µsec Latch hold time (DATA→LATCH) thl 0.5 - - µsec Latch Low setup time ts 0.5 - - µsec Latch Low hold time th 0.5 - - µsec (2) Voltage of control signal (CL, DA, CHIP) Item Conditions Limit Unit Min Typ Max (<VCC) High input voltage VCC=+6.5 to +7.5V VEE=-6.5 to -7.5V 2.3 - 5.5 V Low input voltage 0 - 1.0 V (3) Basic Structure of Control Data ←Input Direction D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data Select Address Figure 10. The timing definition of the control signal CL ( CLOCK) DA DATA LATCH thd thd th ts tsl thl tsd twc twh twd twl tsu DATA DATA LATCH 90% 90% 90% 90% 10% 10% 10% 90% 90% 90% 90% 90% 10% 10% 10% twc |
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