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BD37503FV-E2 Arkusz danych(PDF) 9 Page - Rohm

Numer części BD37503FV-E2
Szczegółowy opis  Sound processor with Built-in 2-band Equalizer
Download  32 Pages
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Producent  ROHM [Rohm]
Strona internetowa  http://www.rohm.com
Logo ROHM - Rohm

BD37503FV-E2 Arkusz danych(HTML) 9 Page - Rohm

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Datasheet
Datasheet
BD37503FV
TSZ02201-0V2V0E100000-1-2
© 2012 ROHM Co., Ltd. All rights reserved.
2013.07.12 Rev.002
www.rohm.co.jp
TSZ22111・15・001
tBUF
:4us
tHD;STA
:2us
tHD;DAT
:1us
tLOW
:3us
tHIGH
:1us
tSU;DAT
:1us
tSU;STO
:2us
SCL clock frequency:250kHz
SCL
SDA
●CONTROL SIGNAL SPECIFICATION
(1) Electrical specifications and timing for bus lines and I/O stages
Figure 14. Definition of timing on the I
2C-bus
Table 1 Characteristics of the SDA and SCL bus lines for I
2C-bus devices
Parameter
Symbol
Fast-mode I
2C-bus
Unit
MIN.
MAX.
1
SCL clock frequency
fSCL
0
400
kHz
2
Bus free time between a STOP and START condition
tBUF
1.3
μS
3
Hold time (repeated) START condition. After this period, the first clock
pulse is generated
tHD;STA
0.6
μS
4
LOW period of the SCL clock
tLOW
1.3
μS
5
HIGH period of the SCL clock
tHIGH
0.6
μS
6
Set-up time for a repeated START condition
tSU;STA
0.6
μS
7
Data hold time
tHD;DAT
0
μS
8
Data set-up time
tSU; DAT
100
ns
9
Set-up time for STOP condition
tSU;STO
0.6
μS
All values referred to VIH min. and VIL max. Levels (see Table 2).
About 7(tHD;DAT), 8(tSU;DAT), please make setup which has enough margin.
Table 2
Characteristics of the SDA and SCL I/O stages for I
2C-bus devices
Item
Symbol
Fast-mode I
2C-bus
Unit
MIN.
MAX.
10
LOW level input voltage: In case an input level is fixed
VIL
-0.5
1
V
11
HIGH level input voltage: In case an input level is fixed
VIH
2.3
-
V
12
Pulse width of spikes which must be suppressed by the input filter.
tSP
0
50
ns
13
LOW level output voltage(open drain or open collector):
at 3mA sink current
VOL1
0
0.4
V
14
Input current each I/O pin with an input voltage between 0.4V and
0.9V.
Ii
-10
10
μA
SDA
S
SCL
tLOW
tR
tHD;DAT
P
tHD;STA
tHIGH
tBUF
tF
tSU;DAT
tSU;STA
tSU;STO
tSP
tHD;STA
Sr
P
Figure 15. A command timing example in the I2C data transmission


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