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54LS168LMQB Arkusz danych(PDF) 1 Page - National Semiconductor (TI) |
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54LS168LMQB Arkusz danych(HTML) 1 Page - National Semiconductor (TI) |
1 / 6 page TLF10207 June 1989 54LS168 Synchronous Bi-Directional BCD Decade Counter General Description The 54LS168 is a fully synchronous 4-state updown coun- ter featuring a preset capability for programmable operation carry lookahead for easy cascading and a UD input to con- trol the direction of counting It counts in the BCD (8421) sequence and all state changes whether in counting or par- allel loading are initiated by the LOW-to-HIGH transition of the clock Connection Diagram Dual-In-Line Package TLF10207 – 1 Order Number 54LS168DMQB 54LS168FMQB or 54LS168LMQB See NS Package Number E20A J16A or W16A Logic Symbol TLF10207 – 2 VCC e Pin 16 GND e Pin 8 Pin Names Description CEP Count Enable Parallel Input (Active LOW) CET Count Enable Trickle Input (Active LOW) CP Clock Pulse Input (Active Rising Edge) P0 – P3 Parallel Data Inputs PE Parallel Enable Input (Active LOW) UD Up-Down Count Control Input Q0 – Q3 Flip-Flop Outputs TC Terminal Count Output (Active LOW) C1995 National Semiconductor Corporation RRD-B30M105Printed in U S A |
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