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MC14027B Arkusz danych(PDF) 1 Page - ON Semiconductor |
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1 / 6 page © Semiconductor Components Industries, LLC, 2014 August, 2014 − Rev. 8 1 Publication Order Number: MC14027B/D MC14027B Dual J-K Flip-Flop The MC14027B dual J−K flip−flop has independent J, K, Clock (C), Set (S) and Reset (R) inputs for each flip−flop. These devices may be used in control, register, or toggle functions. Features • Diode Protection on All Inputs • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Logic Swing Independent of Fanout • Logic Edge−Clocked Flip−Flop Design • Logic State is Retained Indefinitely with Clock Level Either High or Low; Information is Transferred to the Output Only on the Positive−Going Edge of the Clock Pulse • Capable of Driving Two Low−Power TTL Loads or One Low−Power Schottky TTL Load Over the Rated Temperature Range • Pin−for−Pin Replacement for CD4027B • NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable • This Device is Pb−Free and is RoHS Compliant MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol Parameter Value Unit VDD DC Supply Voltage Range − 0.5 to +18.0 V Vin, Vout Input or Output Voltage Range (DC or Transient) − 0.5 to VDD + 0.5 V Iin, Iout Input or Output Current (DC or Transient) per Pin ±10 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Ambient Temperature Range − 55 to +125 °C Tstg Storage Temperature Range − 65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Temperature Derating: “D/DW” Packages: –7.0 mW/ _C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. http://onsemi.com MARKING DIAGRAM SOIC−16 D SUFFIX CASE 751B 14027BG AWLYWW A = Assembly Location WL = Wafer Lot YY, Y = Year WW = Work Week G = Pb−Free Indicator See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ORDERING INFORMATION 1 16 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 RB CB QB QB VDD SB JB KB RA CA QA QA VSS SA JA KA PIN ASSIGNMENT |
Podobny numer części - MC14027B_14 |
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Podobny opis - MC14027B_14 |
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