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MC14042BDR2G Arkusz danych(PDF) 1 Page - ON Semiconductor |
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MC14042BDR2G Arkusz danych(HTML) 1 Page - ON Semiconductor |
1 / 6 page © Semiconductor Components Industries, LLC, 2014 August, 2014 − Rev. 9 1 Publication Order Number: MC14042B/D MC14042B Quad Transparent Latch The MC14042B Quad Transparent Latch is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Each latch has a separate data input, but all four latches share a common clock. The clock polarity (high or low) used to strobe data through the latches can be reversed using the polarity input. Information present at the data input is transferred to outputs Q and Q during the clock level which is determined by the polarity input. When the polarity input is in the logic “0” state, data is transferred during the low clock level, and when the polarity input is in the logic “1” state the transfer occurs during the high clock level. Features • Buffered Data Inputs • Common Clock • Clock Polarity Control • Q and Q Outputs • Double Diode Input Protection • Supply Voltage Range = 3.0 Vdc to 1 8 Vdc • Capable of Driving Two Low−power TTL Loads or One Low−power Schottky TTL Load Over the Rated Temperature Range • NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable • This Device is Pb−Free and is RoHS Compliant MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol Parameter Value Unit VDD DC Supply Voltage Range − 0.5 to +18.0 V Vin, Vout Input or Output Voltage Range (DC or Transient) − 0.5 to VDD + 0.5 V Iin, Iout Input or Output Current (DC or Transient) per Pin ±10 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Ambient Temperature Range − 55 to +125 °C Tstg Storage Temperature Range − 65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Temperature Derating: “D/DW” Packages: –7.0 mW/ _C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. http://onsemi.com MARKING DIAGRAM SOIC−16 D SUFFIX CASE 751B 14042BG AWLYWW A = Assembly Location WL = Wafer Lot YY, Y = Year WW = Work Week G = Pb−Free Indicator See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ORDERING INFORMATION 1 16 PIN ASSIGNMENT 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 Q2 D2 D3 Q3 VDD Q1 Q1 Q2 D0 Q0 Q0 Q3 VSS D1 POLARITY CLOCK |
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Podobny opis - MC14042BDR2G |
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