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ADE7754ARRL Arkusz danych(PDF) 4 Page - Analog Devices

Numer części ADE7754ARRL
Szczegółowy opis  ADE7754
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REV. PrG 01/03
PRELIMINARY TECHNICAL DATA
ADE7754
– 4 –
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADE7754 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
DVDD to AVDD . . . . . . . . . . . . . . . . . . . . . –0.3V to +0.3V
Analog Input Voltage to AGND
IAP,IAN,IBP,IBN,ICP,ICN,VAP,VBP,VCP,VN . –6V to +6V
Reference Input Voltage to AGND –0.3V to AVDD+0.3V
Digital Input Voltage to DGND .
–0.3V to DVDD+0.3V
Digital Output Voltage to DGND –0.3V to DVDD+0.3V
Operating Temperature Range
Industrial . . . . . . . . . . . . . . . . . . . . . . .
–40°C to +85°C
Storage Temperature Range . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . .
+150°C
24-Lead SOIC, Power Dissipation . . . . . . . . .
TBD mW
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . .
53°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . .
+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . .
+220°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Terminology
MEASUREMENT ERROR
The error associated with the energy measurement made by
the ADE7754 is defined by the following formula:
Percentage Error
Energy registered by ADE
True Energy
True En
=
7754
eergy
×


100%
PHASE ERROR BETWEEN CHANNELS
The HPF (High Pass Filter) in the current channel has a
phase lead response. To offset this phase response and
equalize the phase response between channels a phase correc-
tion network is also placed in the current channel. The phase
correction network ensures a phase match between the
current channels and voltage channels to within ±0.1° over a
range of 45Hz to 65Hz and ±0.2° over a range 40Hz to 1kHz.
This phase mismatch between the voltage and the current
channels can be further reduced with the phase calibration
register in each phase.
POWER SUPPLY REJECTION
This quantifies the ADE7754 measurement error as a per-
centage of reading when the power supplies are varied.
For the AC PSR measurement a reading at nominal supplies
(5V) is taken. A second reading is obtained with the same
input signal levels when an ac (175mVrms/100Hz) signal is
introduced onto the supplies. Any error introduced by this ac
signal is expressed as a percentage of reading—see Measure-
ment Error definition above.
For the DC PSR measurement a reading at nominal supplies
(5V) is taken. A second reading is obtained with the same
input signal levels when the power supplies are varied ±5%.
Any error introduced is again expressed as a percentage of
reading.
ADC OFFSET ERROR
This refers to the DC offset associated with the analog inputs
to the ADCs. It means that with the analog inputs connected
to AGND the ADCs still see a dc analog input signal. The
magnitude of the offset depends on the gain and input range
selection - see characteristic curves. However, when HPFs
are switched on the offset is removed from the current
channels and the power calculation is not affected by this
offset.
GAIN ERROR
The gain error in the ADE7754 ADCs, is defined as the
difference between the measured ADC output code (minus
the offset) and the ideal output code - see Current Channel ADC
& Voltage Channel ADC. The difference is expressed as a
percentage of the ideal code.
GAIN ERROR MATCH
The Gain Error Match is defined as the gain error (minus the
offset) obtained when switching between a gain of 1, 2 or 4.
It is expressed as a percentage of the output ADC code
obtained under a gain of 1.


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