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MC14043B Arkusz danych(PDF) 1 Page - ON Semiconductor |
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MC14043B Arkusz danych(HTML) 1 Page - ON Semiconductor |
1 / 7 page © Semiconductor Components Industries, LLC, 2014 August, 2014 − Rev. 10 1 Publication Order Number: MC14043B/D MC14043B, MC14044B CMOS MSI Quad R−S Latches The MC14043B and MC14044B quad R−S latches are constructed with MOS P−Channel and N−Channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three−state buffers having a common enable input. The outputs are enabled with a logical “1” or high on the enable input; a logical “0” or low disconnects the latch from the Q outputs, resulting in an open circuit at the Q outputs. Features • Double Diode Input Protection • Three−State Outputs with Common Enable • Outputs Capable of Driving Two Low−power TTL Loads or One Low−Power Schottky TTL Load Over the Rated Temperature Range • Supply Voltage Range = 3.0 Vdc to 18 Vdc • NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable • These Devices are Pb−Free and are RoHS Compliant MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol Parameter Value Unit VDD DC Supply Voltage Range − 0.5 to +18.0 V Vin, Vout Input or Output Voltage Range (DC or Transient) − 0.5 to VDD + 0.5 V Iin, Iout Input or Output Current (DC or Transient) per Pin ±10 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Ambient Temperature Range − 55 to +125 °C Tstg Storage Temperature Range − 65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Temperature Derating: “D/DW” Packages: –7.0 mW/ _C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. http://onsemi.com MARKING DIAGRAMS SOIC−16 140xxBG AWLYWW xx = Specific Device Code A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = Pb−Free Indicator SOEIAJ−16 MC14043B ALYWG See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ORDERING INFORMATION 1 16 1 16 SOIC−16 D SUFFIX CASE 751B SOEIAJ−16 F SUFFIX CASE 966 |
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