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FW802C Arkusz danych(PDF) 8 Page - Agere Systems

Numer części FW802C
Szczegółowy opis  FW 802C LOW - POWER IEEE 1394A-2000 TWO CABLE TRANSCEIVER/ ARBITER DEVICE
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Agere Systems Inc.
Data Sheet, Rev. 1
October 2002
Two-Cable Transceiver/Arbiter Device
FW802C Low-Power PHY
IEEE 1394A-2000
Signal Information (continued)
Table 1. Signal Descriptions (continued)
Pin
Signal*
Type
Name/Description
14
LPS
I
Link Power Status. LPS is connected to either the VDD supplying the
LLC or to a pulsed output that is active when the LLC is powered for the
purpose of monitoring the LLC power status. If LPS is inactive for more
than 1.2
µs and less than 25 µs, interface is reset. If LPS is inactive for
greater than 25
µs, the PHY will disable the PHY/Link interface to save
power. FW802C continues its repeater function.
48
LREQ
I
Link Request. LREQ is an output from the LLC that requests the PHY to
perform some service. Bus-keeper circuitry is built into this terminal.
18
PD
I
Powerdown. When asserted high, PD turns off all internal circuitry except
the bias-detect circuits that drive the CNA signal. Internal FW802C logic is
kept in the reset state as long as PD is asserted. PD terminal is provided
for backward compatibility. It is recommended that the FW802C be
allowed to manage its own power consumption using suspend/resume in
conjunction with LPS. C/LKON features are defined in
1394a-2000.
41
PLLVDD
Power for PLL Circuit. PLLVDD supplies power to the PLL circuitry
portion of the device.
42
PLLVSS
Ground for PLL Circuit. PLLVSS is tied to a low-impedance ground
plane.
37
R0
I
Current Setting Resistor. An internal reference voltage is applied to a
resistor connected between R0 and R1 to set the operating current and
the cable driver output current. A low temperature-coefficient resistor
(TCR) with a value of 2.49 k
Ω ± 1% should be used to meet the
IEEE 1394-1995 standard requirements for output voltage limits.
38
R1
45
/RESET
I
Reset (Active-Low). When /RESET is asserted low (active), the FW802C
is reset. An internal pull-up resistor, which is connected to VDD, is
provided, so only an external delay capacitor is required. This input is a
standard logic buffer and can also be driven by an open-drain logic output
buffer.
21
SE
I
Test Mode Control. SE is used during the manufacturing test and should
be tied to VSS.
22
SM
I
Test Mode Control. SM is used during the manufacturing test and should
be tied to VSS.
46
SYSCLK
O
System Clock. SYSCLK provides a 49.152 MHz clock signal, which is
synchronized with the data transfers to the LLC.
28
TPA0+
Analog I/O Portn, Port Cable Pair A. TPAn is the port A connection to the twisted-
pair cable. Board traces from each pair of positive and negative differen-
tial signal pins should be kept matched and as short as possible to the
external load resistors and to the cable connector.
34
TPA1+
27
TPA0
Analog I/O Portn, Port Cable Pair A. TPAn is the port A connection to the twisted-
pair cable. Board traces from each pair of positive and negative differen-
tial signal pins should be kept matched and as short as possible to the
external load resistors and to the cable connector.
33
TPA1
26
TPB0+
Analog I/O Portn, Port Cable Pair B. TPBn is the port B connection to the twisted-
pair cable. Board traces from each pair of positive and negative differen-
tial signal pins should be kept matched and as short as possible to the
external load resistors and to the cable connector.
32
TPB1+
* Active-low signals are indicated by “/” at the beginning of signal names, within this document.


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