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KM6164000BLTI-7L Arkusz danych(PDF) 8 Page - Samsung semiconductor

Numer części KM6164000BLTI-7L
Szczegółowy opis  256Kx16 bit Low Power CMOS Static RAM
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Producent  SAMSUNG [Samsung semiconductor]
Strona internetowa  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

KM6164000BLTI-7L Arkusz danych(HTML) 8 Page - Samsung semiconductor

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KM6164000B Family
CMOS SRAM
Revision 4.01
June 1998
8
Address
CS
Data Valid
UB, LB
WE
Data in
Data out
High-Z
High-Z
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-
tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high.
tWC
tCW(2)
tBW
tWP(1)
tDH
tDW
tWR(4)
tAW
DATA RETENTION WAVE FORM
CS controlled
VCC
4.5V
2.2V
VDR
CS
GND
Data Retention Mode
CS
≥VCC - 0.2V
tSDR
tRDR
tAS(3)


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