MC14LC5540

MOTOROLA

7

DR

4

3

2

1

4

3

2

1

DT

BCLKT (BCLKR)

FST (FSR)

DON’T CARE

DON’T CARE

Figure 5. Short Frame Sync (32 kbps ADPCM Data Timing)

A3

D0

D1

D2

D3

D4

D5

D6

D7

A0

A1

A2

R/W

SCP Tx

SCP Rx

SCPCLK

SCPEN

DON’T CARE

HIGH IMPEDANCE

DON’T CARE

Figure 6. SCP Byte Register Write Operation Using Double 8–Bit Transfer

A3

D0

D1

D2

D3

D4

D5

D6

D7

A0

A1

A2

R/W

SCP Tx

SCP Rx

SCPCLK

SCPEN

DON’T CARE

DON’T CARE

HIGH IMPEDANCE

Figure 7. SCP Byte Register Read Operation Using Double 8–Bit Transfer

A3

D0

D1

D2

D3

D4

D5

D6

D7

A0

A1

A2

DON’T CARE

DON’T CARE

SCP Tx

SCP Rx

SCPCLK

SCPEN

R/W

HIGH IMPEDANCE

Figure 8. SCP Byte Register Write Operation Using Single 16–Bit Transfer