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MC14LC5540FU Arkusz danych(PDF) 11 Page - Motorola, Inc |
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MC14LC5540FU Arkusz danych(HTML) 11 Page - Motorola, Inc |
11 / 18 page MC14LC5540 MOTOROLA 11 connecting the external 0.1 µF capacitor (C1) between the VEXT power supply pin and the power supply ground pin, VSS. This puts a charge of as much as 2.7 V on C1. The charge pump circuitry then connects the negative lead of C1 to the VEXT, pin which sums the voltage of C1 with the volt- age at VEXT for a minimum potential voltage of 5.4 V. The charge voltage on C1 is regulated such that the summing of voltages is regulated to 5 V. This limits all of the voltages on the device to safe levels for this IC fabrication technology. This charge pumped voltage is then stored on the 1.0 µF ca- pacitor connected at VDD and VSS, which filters and serves as a reservoir for power. The clock period for this charge pump is the same 256 kHz as the analog sequencing clock, minimizing noise problems. For applications with a regulated 5 V ( ± 5%) power supply, the VDD pin and the VEXT pin are connected to the 5 V power supply. These pins may share one decoupling capacitor in this configuration as a function of external noise on the power supply. The on–chip, 5 V regulated charge pump should be turned off via the SCP port at register 0. The external capacitor (C1) should not be populated for these applications. Digital Signal Processing Power Supply This device has an on–chip series regulator which limits the voltage of the Digital Signal Processing (DSP) circuitry to about 2.3 V. This reduces the maximum power dissipation of this circuitry. From the VEXT power supply pin, the DSP cir- cuitry appears as a constant current load instead of a resis- tive (CV2 / 2) load for a constant clock frequency. This series regulator is designed to have a low drop–out voltage, which allows the DSP circuitry to work when the VEXT voltage is as low as 2.7 V. The output of this regulator is brought out to the VDSP pin for a 0.1 µF decoupling capacitor. This regulator is not designed to power any loads external to the device. ANALOG INTERFACE AND SIGNAL PATH Transmit Analog The transmit analog portion of this device includes a low– noise, three terminal operational amplifier capable of driving a 2 k Ω load. This op amp has inputs of TI+ and TI– and its output is TG. This op amp is intended to be configured in an inverting gain circuit. The analog signal may be applied di- rectly to the TG pin if this transmit op amp is independently powered down. Power–down may be achieved by connect- ing both the TI+ and TI– inputs to the VDD pin. The TG pin becomes high impedance when the transmit op amp is pow- ered down. The TG pin is internally connected to a time con- tinuous three–pole anti–aliasing pre–filter. This pre–filter incorporates a two–pole Butterworth active low–pass filter, followed by a single passive pole. This pre–filter is followed by a single–ended to differential converter that is clocked at 512 kHz. All subsequent analog processing utilizes fully dif- ferential circuitry. The output of the differential converter is followed by the transmit trim gain stage. This stage is in- tended to compensate for gain tolerances of external compo- nents such as microphones. The amount of gain control is 0–7 dB in 1 dB steps. This stage only accommodates posi- tive gain because the maximum signal levels of the output of the input op amp are the same as the transmit filter and ADC, which should nominally be next to the clip levels of this de- vice’s circuitry. Any requirement for attenuation of the output of the input op amp would mean that it is being overdriven. The gain is programmed via the SCP port in BR1 (b2:b0). The next section is a fully–differential, 5–pole switched–ca- pacitor low–pass filter with a 3.4 kHz frequency cutoff. After this filter is a 3–pole switched–capacitor high–pass filter hav- ing a cutoff frequency of about 200 Hz. This high–pass stage has a transmission zero at dc that eliminates any dc coming from the analog input or from accumulated op amp offsets in the preceding filter stages. (This high–pass filter may be re- moved from the signal path under control of the SCP port BR8 (b4).) The last stage of the high–pass filter is an auto- zeroed sample and hold amplifier. One bandgap voltage reference generator and digital–to– analog converter (DAC) are shared by the transmit and receive sections. The autozeroed, switched–capacitor band- gap reference generates precise positive and negative refer- ence voltages that are virtually independent of temperature and power supply voltage. A binary–weighted capacitor array (CDAC) forms the chords of the companding structure, while a resistor string (RDAC) implements the linear steps within each chord. The encode process uses the DAC, the voltage reference, and a frame–by–frame autozeroed comparator to implement a successive–approximation ana- log–to–digital conversion (ADC) algorithm. All of the analog circuitry involved in the data conversion (the voltage refer- ence, RDAC, CDAC, and comparator) are implemented with a differential architecture. The nonlinear companded Mu–Law transfer curve of the ADC may be changed to 8–bit linear by BR8 (b5). The input to the ADC is normally connected to the output of the transmit filter section, but may be switched to measure the voltage at the VEXT pin for battery voltage monitoring. This is selected by the I/O Mode in BR0 (b4:b3). In this mode, the ADC is programmed to output a linear 8–bit PCM word for the voltage at VEXT which is intended to be read in BR9 (b7:b0). The data format for the ADC output is a “Don’t Care” for the sign bit and seven magnitude bits. The scaling for the ADC is for 6.3 V at VEXT equals full scale (BIN X111 1111). The ADPCM algorithm does not support dc signals. Transmit Digital The Digital Signal Processor (DSP) section of this device is a custom designed, interrupt driven, microcoded machine optimized for implementing the ADPCM algorithms. In the full–duplex speech mode, the DSP services one encode in- terrupt and one decode interrupt per frame (125 µs). The en- code algorithm (i.e., 16 kbps, 24 kbps, or 32 kbps ADPCM, or 64 kbps PCM) is determined by the length of the transmit output enable at the FST pin. The length of the FST enable measured in transmit data clock (BCLKT) cycles tells the de- vice which encoding rate to use. This enable length informa- tion is used by the encoder each frame. The transmit ADPCM word corresponding to this request will be computed during the next frame and will be available a total of two frames after being requested. This transmit enable length in- formation can be delayed by the device an additional four frames corresponding to a total of six frames. These six frames of delay allow the device to be clocked with the same clocks for both transmit (encode) and receive (decode), and to be frame aligned for applications that require every sixth frame signaling. It is important to note that the enable length information is delayed and not the actual ADPCM (PCM) sample word. The amount of delay for the FST enable length |
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