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AD6684-500EBZ Arkusz danych(PDF) 1 Page - Analog Devices

Numer części AD6684-500EBZ
Szczegółowy opis  135 MHz Quad IF Receiver
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
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AD6684-500EBZ Arkusz danych(HTML) 1 Page - Analog Devices

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135 MHz Quad IF Receiver
Data Sheet
AD6684
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
FEATURES
JESD204B (Subclass 1) coded serial digital outputs
Lane rates up to 15 Gbps
1.68 W total power at 500 MSPS
420 mW per analog-to-digital converter (ADC) channel
SFDR = 82 dBFS at 305 MHz (1.8 V p-p input range)
SNR = 66.8 dBFS at 305 MHz (1.8 V p-p input range)
Noise density = −151.5 dBFS/Hz (1.8 V p-p input range)
Analog input buffer
On-chip dithering to improve small signal linearity
Flexible differential input range
1.44 V p-p to 2.16 V p-p (1.80 V p-p nominal)
82 dB channel isolation/crosstalk
0.975 V, 1.8 V, and 2.5 V dc supply operation
Noise shaping requantizer (NSR) option for main receiver
Variable dynamic range (VDR) option for digital
predistortion (DPD)
4 integrated wideband digital downconverters (DDCs)
48-bit numerically controlled oscillator (NCO), up to
4 cascaded half-band filters
1.4 GHz analog input full power bandwidth
Amplitude detect bits for efficient automatic gain control
(AGC) implementation
Differential clock input
Integer clock divide by 1, 2, 4, or 8
On-chip temperature diode
Flexible JESD204B lane configurations
APPLICATIONS
Communications
Diversity multiband, multimode digital receivers
3G/4G, W-CDMA, GSM, LTE, LTE-A
HFC digital reverse path receivers
Digital predistortion observation paths
General-purpose software radios
FUNCTIONAL BLOCK DIAGRAM
CLK+
CLK–
SDIO SCLK CSB
AGND
AD6684
SYSREF±
CLOCK
GENERATION
14
SPI CONTROL
14
14
14
2
PDWN/STBY
JESD204B
SUBCLASS 1
CONTROL
FAST
DETECT
VIN+B
VIN–B
÷2
÷4
ADC
CORE
BUFFER
ADC
CORE
SIGNAL
MONITOR
SYNCINB±AB
VIN+C
VIN–C
FD_C
FD_D
SERDOUTCD0±
SERDOUTCD1±
SERDOUTAB0±
SERDOUTAB1±
VIN+D
VIN–D
SIGNAL PROCESSING
Tx
OUTPUTS
JESD204B
HIGH SPEED
SERIALIZER
SYNCINB±CD
AVDD1
(0.975V)
AVDD2
(1.8V)
DRVDD1
(0.975V)
DVDD
(0.975V)
AVDD3
(2.5V)
AVDD1_SR
(0.975V)
SPIVDD
(1.8V)
DRVDD2
(1.8V)
DIGITAL DOWNCONVERTER
(×2)
NOISE SHAPED REQUANTIZER
(×2)
VARIABLE DYNAMIC RANGE
(×2)
BUFFER
2
FAST
DETECT
ADC
CORE
BUFFER
ADC
CORE
SIGNAL
MONITOR
SIGNAL PROCESSING
Tx
OUTPUTS
JESD204B
HIGH SPEED
SERIALIZER
DIGITAL DOWNCONVERTER
(×2)
NOISE SHAPED REQUANTIZER
(×2)
VARIABLE DYNAMIC RANGE
(×2)
BUFFER
DRGND
VIN+A
VIN–A
VCM_AB
VCM_CD
FD_A
FD_B
÷8
SIGNAL MONITOR
AND FAST DETECT
Figure 1.


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