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ADM2795EARWZ Arkusz danych(PDF) 8 Page - Analog Devices |
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ADM2795EARWZ Arkusz danych(HTML) 8 Page - Analog Devices |
8 / 27 page ADM2795E Data Sheet Rev. 0 | Page 8 of 27 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 10. Pin Function Descriptions Pin No. Mnemonic Description 1 V DD1 1.7 V to 5.5 V Flexible Logic Interface Supply. 2 GND 1 Ground 1, Logic Side. 3 TxD Transmit Data Input. Data to be transmitted by the driver is applied to this input. 4 DE Driver Output Enable. A high level on this pin enables the driver differential outputs, A and B. A low level places them into a high impedance state. 5 RE Receiver Enable Input. This pin is an active low input. Driving this input low enables the receiver, and driving it high disables the receiver. 6 RxD Receiver Output Data. This output is high when (A – B) > −30 mV and low when (A – B) < –200 mV. 7 NIC Not Internally Connected. This pin is not internally connected. 8 GND 1 Ground 1, Logic Side. 9 GND 2 Isolated Ground 2, Bus Side. 10 GND 2 Isolated Ground 2, Bus Side. 11 A Noninverting Driver Output/Receiver Input. When the driver is disabled, or when V DD1 or VDD2 is powered down, Pin A is put into a high impedance state to avoid overloading the bus. 12 GND 2 Isolated Ground 2, Bus Side. 13 V DD2 3 V to 5.5 V Power Supply. Pin 13 must be connected externally to Pin 16. 14 B Inverting Driver Output/Receiver Input. When the driver is disabled, or when V DD1 or VDD2 is powered down, Pin B is put into a high impedance state to avoid overloading the bus. 15 GND 2 Isolated Ground 2, Bus Side. 16 V DD2 3 V to 5.5 V Power Supply. Pin 16 must be connected externally to Pin 13. VDD1 1 GND1 2 TxD 3 DE 4 VDD2 16 GND2 15 B 14 VDD2 13 RE 5 GND2 12 RxD 6 A 11 NIC NOTES 1. NIC = NOT INTERNALLY CONNECTED. 7 GND2 10 GND1 8 GND2 9 ADM2795E (Not to Scale) TOP VIEW |
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