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Si531 Arkusz danych(PDF) 2 Page - Silicon Laboratories |
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Si531 Arkusz danych(HTML) 2 Page - Silicon Laboratories |
2 / 2 page Process Change Notice #1106071 ____________________________________________________________________________________________________ W7206F1 Process Change Notice Form rev AA The information contained in this document is PROPRIETARY to Silicon Laboratories, Inc. and shall not be reproduced or used in part or whole without Silicon Laboratories’ written consent. The document is uncontrolled if printed or electronically saved. Pg 2 Appendix A: Si530/31 datasheet revision 1.1 to v1.2 changes: Updated 2.5 V/3.3 V and 1.8 V CML output level specifications for Table 3 on page 3. Added footnotes clarifying max offset frequency test conditions for Table 4 on page 4. Added CMOS phase jitter specs to Table 4 on page 4. Removed the words "Differential Modes: LVPECL/LVDS/CML" in footnote referring to AN256 in Table 4 on page 4. Separated 1.8 V, 2.5 V/3.3 V supply voltage specifications in Table 8 on page 5. Updated and clarified Table 8 on page 5 to include the "Moisture Sensitivity Level" and "Contact Pads" rows. Updated Figure 3 on page 9 and Table 12 on page 9 to reflect specific marking information. Previously, Figure 3 was generic. Si532 datasheet revision 1.1 to v1.2 changes: Updated 2.5 V/3.3 V and 1.8 V CML output level specifications for Table 3 on page 3. Added footnotes clarifying max offset frequency test conditions for Table 4 on page 4. Removed the words "Differential Modes: LVPECL/LVDS/CML" in footnote referring to AN256 in Table 4 on page 4. Added CMOS phase jitter specs to Table 4 on page 4. Updated Table 8 on page 5 to include the "Moisture Sensitivity Level" and "Contact Pads" rows. Updated Figure 3 and Table 11 on page 9 to reflect specific marking information. Previously, Figure 3 was generic. Si533 datasheet revision 1.1 to v1.2 changes: Updated 2.5 V/3.3 V and 1.8 V CML output level specifications for Table 3 on page 3. Added footnotes clarifying max offset frequency test conditions for Table 4 on page 4. Removed the words "Differential Modes: LVPECL/LVDS/CML" in footnote referring to AN256 in Table 4 on page 4. Added CMOS phase jitter specs to Table 4 on page 4. Updated Table 8 on page 5 to include the "Moisture Sensitivity Level" and "Contact Pads" rows. Updated Figure 3 and Table 10 on page 9 to reflect specific marking information. Previously, Figure 3 was generic. Updated contact information on page 12. Si533 datasheet revision 1.1 to v1.2 changes: Updated 2.5 V/3.3 V and 1.8 V CML output level specifications for Table 3 on page 3. Added footnotes clarifying max offset frequency test conditions for Table 4 on page 4. Removed the words "Differential Modes: LVPECL/LVDS/CML" in footnote referring to AN256 in Table 4 on page 4. Added CMOS phase jitter specs to Table 4 on page 4. Updated ESD HBM sensitivity rating in Table 7 on page 5. Updated Table 8 on page 5 to include the "Moisture Sensitivity Level" and "Contact Pads" rows. Updated package diagram to include crystal impedance pin in Figure 2 on page 8. Updated Figure 3 and Table 11 on page 9 to reflect specific marking information. Previously, Figure 3 was generic. Access to online datasheets: Si530/31 Datasheet v1.2 can be found here: http://www.silabs.com/Support%20Documents/TechnicalDocs/si530.pdf Si532 Datasheet v1.2 can be found here: http://www.silabs.com/Support%20Documents/TechnicalDocs/si532.pdf Si533 Datasheet v1.2 can be found here: http://www.silabs.com/Support%20Documents/TechnicalDocs/si533.pdf Si534 Datasheet v1.2 can be found here: http://www.silabs.com/Support%20Documents/TechnicalDocs/si534.pdf |
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