2. Functional Description

The Si53340-45 are a family of low-jitter, low skew, fixed format (LVDS) buffers. The Si53340/42/44 have a universal input that accepts

most common differential or LVCMOS input signals, while the Si53341/43/45 accept only LVCMOS inputs. These devices are available

in multiple configurations customized for the end application (refer to 1. Ordering Guide for more details on configurations).

2.1 Universal, Any-Format Input Termination (Si53340/42/44)

The universal input stage enables simple interfacing to a wide variety of clock formats, including LVPECL, Low-power LVPECL, LVDS,

CML, HCSL, and LVCMOS. The tables below summarize the various ac- and dc-coupling options supported by the device. For the best

high-speed performance, the use of differential formats is recommended. For both single-ended and differential input clocks, the fastest

possible slew rate is recommended since low slew rates can increase the noise floor and degrade jitter performance. Though not re-

quired, a minimum slew rate of 0.75 V/ns is recommended for differential formats and 1.0 V/ns for single-ended formats. See “AN766:

Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information.

Table 2.1. Clock Input Options

Clock Format

1.8 V

2.5/3.3 V

AC-Coupled

LVPECL/Low-power LVPECL

N/A

Yes

LVCMOS

No

Yes

LVDS

Yes

Yes

HCSL

No

Yes (3.3 V)

CML

Yes

Yes

DC-Coupled

LVPECL/Low-power LVPECL

N/A

Yes

LVCMOS

No

Yes

LVDS

No

Yes

HCSL

No

Yes (3.3 V)

CML

No

No

Si53340-45 Data Sheet

Functional Description

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