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SL28PCIE50 Arkusz danych(PDF) 8 Page - Silicon Laboratories |
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SL28PCIE50 Arkusz danych(HTML) 8 Page - Silicon Laboratories |
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8 / 17 page  SL28PCIe50 DOC#: SP-AP-0758 (Rev. AA) Page 8 of 16 Input Pins Clearification SRC_EN Clarification SRC_EN pin is a 3.3V active high input pin. When the SRC_EN signal is a logic low, all SRC clocks will be disabled sychronously regardless of the CLKREQ# state. If SRC_EN pin remains disabled it can be re-enabled through the SMBus register. The SRC_EN signal will be asserted high whenever the SRC_EN pin or the SRC_EN bit is a logic high. CLKREQ# Clarification The CLKREQ# signals are active low inputs used to cleanly enable and disabe selected SRC outputs. If CLKREQ# pin remains disabled it can be re-enabled through the SMBus register. The CLKREQ# signal will be asserted high whenever the CLKREQ# pin or the CLKREQ# bit is a logic high. OE Clarification The OE signals are active high inputs used to enable and disabe single-ended outputs. If OE pin remains disabled it can be re-enabled through the SMBus register. The OE signal will be asserted high whenever the OE pin or the OE bit is a logic high. OE pins is required to be driven at all time. RESET# Clarification The RESET# signal is 3.3V output signal with an internal 100k-ohm pull-down. The RESET# output is low during power up. When SRC_EN is low and after all SRC clocks go low, RESET# will go low. If any of the SRCs is running when SRC_EN is low, RESET# will not go low. When PD pin is de-asserted and SRC_EN goes high, RESET# will remain low for 100ms then goes high. If PD is asserted, RESET# will be low. Byte 7: Control Register 7 Bit @Pup Type Name Description 7 0 R/W PLL2_SS_EN Spread Enabled for PLL2 0=Spread Disabled; 1=Spread Enabled 6 0 R/W CONFIG_SE1_FS2 See Table 6 on page 7 for full configuraiton 5 0 R/W CONFIG_SE1_FS1 4 0 R/W CONFIG_SE1_FS0 3 0 R/W PLL1_PD Power Down PLL1 0=Enabled PLL1; 1=Disabled PLL1 2 0 R/W PLL2_PD Power Down PLL2 0=Enabled PLL2; 1=Disabled PLL2 1 0 R/W PLL3_PD Power Down PLL3 0=Enabled PLL3; 1=Disabled PLL3 0 1 R/W RESET#_SET RESET# Output setting 0=RESET# output goes low, but will not disabled SRC clocks 1=RESET# goes high after 100ms if device is not in power down or SRC_EN in not “0” Table 4. CLKREQ# Table for SRC Clocks CKPWRGD / PD# SRC_EN Pin SRC_EN Bit CLKREQ# Pin CLKREQ# Bit SRC Clocks 11 X 0 X Enabled 11 X X 0 Enabled 1X 1 0 X Enabled 1X 1 X 0 Enabled 1 0 0 0 0 Disabled if not free running 1 0 0 0 1 Disabled if not free running 1 0 0 1 0 Disabled if not free running 1 X X 1 1 Disabled 0 X X X X Disabled |
Podobny numer części - SL28PCIE50 |
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Podobny opis - SL28PCIE50 |
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