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SL28PCIE50 Arkusz danych(PDF) 3 Page - Silicon Laboratories |
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SL28PCIE50 Arkusz danych(HTML) 3 Page - Silicon Laboratories |
3 / 17 page SL28PCIe50 DOC#: SP-AP-0758 (Rev. AA) Page 3 of 16 EProClock® Programmable Technology EProClock® is the world’s first non-volatile programmable clock. The EProClock® technology allows board designer to promptly achieve optimum compliance and clock signal integrity; historically, attainable typically through device and/or board redesigns. EProClock® technology can be configured through SMBus or hard coded. Features: - > 4000 bits of configurations - Can be configured through SMBus or hard coded - Custom frequency sets - Differential skew control on true or compliment or both - Differential duty cycle control on true or compliment or both - Differential amplitude control - Differential and single-ended slew rate control - Program Internal or External series resistor on single-ended clocks - Programmable different spread profiles - Programmable modulation rates Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers are individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting at power-up. The use of this interface is optional. Clock device register changes are normally made at system initialization, if any are required. The interface cannot be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, access the bytes in sequential order from lowest to highest (most significant bit first) with the ability to stop after any complete byte is transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code described in Table 1. The block write and block read protocol is outlined in Table 2 while Table 3 outlines byte write and byte read protocol. The slave receiver address is 11010010 (D2h). 42 CKPWRGD/PD# I 3.3V LVTTL input. This pin is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled /this pin becomes a real-time active low input for asserting power down (PD#) 43 VDD_SE1 PWR 3.3V Power Supply for CONF_SE1 clock 44 CONF_SE1 O, SE 3.3V, configurable single-ended clock 45 VSS_SE1 GND Ground for CONFI_SE1 clock 46 CLKREQ#1* I, PU 3.3V, active low input clock request to enable SRC1 (internal 100k-ohm internal pull-up) 47 CLKREQ#2* I, PU 3.3V, active low input clock request to enable SRC2 (internal 100k-ohm internal pull-up) 48 OE_CONF_SE1 I 3.3V, active high input clock request to enable CONF_SE1 Pin No. Name Type Description Table 1. Command Code Definition Bit Description 7 0 = Block read or block write operation, 1 = Byte read or byte write operation (6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 2. Block Read and Block Write Protocol Block Write Protocol Block Read Protocol Bit Description Bit Description 1Start 1 Start 8:2 Slave address–7 bits 8:2 Slave address–7 bits |
Podobny numer części - SL28PCIE50 |
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Podobny opis - SL28PCIE50 |
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