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MC12439 Arkusz danych(PDF) 8 Page - Motorola, Inc |
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MC12439 Arkusz danych(HTML) 8 Page - Motorola, Inc |
8 / 11 page MC12439 MOTOROLA TIMING SOLUTIONS BR1333 — Rev 6 8 A higher level of attenuation can be acheived by replacing the resistor with an appropriate valued inductor. A 1000 µH choke will show a significant impedance at 10KHz frequencies and above. Because of the current draw and the voltage that must be maintained on the PLL_VCC pin a low DC resistance inductor is required (less than 15 Ω). Generally the resistor/capacitor filter will be cheaper, easier to implement and provide an adequate level of supply filtering. The MC12439 provides sub–nanosecond output edge rates and thus a good power supply bypassing scheme is a must. Figure 6 shows a representaive board layout for the MC12439. There exists many different potential board layouts and the one pictured is but one. The important aspect of the layout in Figure 6 is the low impedance connections between VCC and GND for the bypass capacitors. Combining good quality general purpose chip capacitors with good PCB layout techniques will produce effective capacitor resonances at frequencies adequate to supply the instantaneous switching current for the 12439 outputs. It is imperative that low inductance chip capacitors are used; it is equally important that the board layout does not introduce back all of the inductance saved by using the leadless capacitors. Thin interconnect traces between the capacitor and the power plane should be avoided and multiple large vias should be used to tie the capacitors to the buried power planes. Fat interconnect and large vias will help to minimize layout induced inductance and thus maximize the series resonant point of the bypass capacitors. Figure 6. PCB Board Layout for MC12439 C2 1 C3 R1 Xtal C1 C1 R1 = 10–15 Ω C1 = 0.01 µF C2 = 22 µF C3 = 0.1 µF = VCC = GND = Via Note the dotted lines circling the crystal oscillator connection to the device. The oscillator is a series resonant circuit and the voltage amplitude across the crystal is relatively small. It is imperative that no actively switching signals cross under the crystal as crosstalk energy coupled to these lines could significantly impact the jitter of the device. Special attention should be paid to the layout of the crystal to ensure a stable, jitter free interface between the crystal and the on–board oscillator. Although the MC12439 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter and bypass schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Jitter Performance of the MC12439 The MC12439 exhibits long term and cycle–to–cycle jitter which rivals that of SAW based oscillators. This jitter performance comes with the added flexibility one gets with a synthesizer over a fixed frequency oscillator. Figure 7. RMS PLL Jitter versus VCO Frequency 0 5 10 15 20 25 400 500 600 700 800 N=2 N=4 N=8 VCO Frequency (MHz) NO TAG illustrates the RMS jitter performance of the MC12439 across its specified VCO frequency range. Note that the jitter is a function of both the output frequency as well as the VCO frequency, however the VCO frequency shows a much stronger dependence. The data presented has not been compensated for trigger jitter, this fact provides a measure of guardband to the reported data. In addition the data represents long term period jitter, the cycle–to–cycle jitter could not be measured to the level of accuracy required with available test equipment but certainly will be smaller than the long term period jitter. The most commonly specified jitter parameter is cycle–to–cycle jitter. Unfortunately with today’s high performance measurement equipment there is no way to measure this parameter for jitter performance in the class demonstrated by the MC12439. As a result different methods are used which approximate cycle–to–cycle jitter. The typical method of measuring the jitter is to accumulate a large number of cycles, create a histogram of the edge placements and record peak–to–peak as well as standard deviations of the jitter. Care must be taken that the measured edge is the edge immediately following the trigger edge. The oscilloscope cannot collect adjacent pulses, rather it collects pulses from a very large sample of pulses. It is safe to assume that collecting pulse information in this mode will produce period jitter values somewhat larger than if consecutive cycles (cycle–to–cycle jitter) were measured. All of the jitter data reported on the MC12439 was collected in this manner. |
Podobny numer części - MC12439 |
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Podobny opis - MC12439 |
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