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MC14508BDW Arkusz danych(PDF) 5 Page - Motorola, Inc |
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MC14508BDW Arkusz danych(HTML) 5 Page - Motorola, Inc |
5 / 7 page MOTOROLA CMOS LOGIC DATA MC14508B 348 3–STATE MODE OF OPERATION The MC14508B can be used in bussed systems as shown. The output terminals of N 4–bit latches can be directly wired to a bus line, and to one of the 4–bit latches selected. The selected latch controls the logic state of the bus line and the remaining (N–1) 4–bit latches are disabled into a high imped- ance “off” state. The number of latches, N, which may be connected to a bus line is determined from the output drive current, IOD, the 3–state or disabled output leakage current, ITL, and the load current, IL, required to drive the bus line (in- cluding fanout to other device inputs) and can be calculated by the following: ITL N = + 1 IOD – IL N must be calculated for both high and low logic states of the bus line. SELECTED AS DRIVING DEVICE 1/2 MC14508B DISABLED 1/2 MC14508B DISABLED 1/2 MC14508B IOD IOD ITL ITL ITL ITL IL IL BUS LINES TYPICAL 3–STATE APPLICATIONS EXAMPLE 1 EXAMPLE 2 DISABLE DISABLE STROBE SERIAL DATA CLOCK RESET 4–LINE DATA BUS MC14015B MC 14508B 4–BIT SHIFT REGISTER 4–BIT SHIFT REGISTER QUAD LATCH (3–STATE) QUAD LATCH (3–STATE) 3–STATE 4–BIT LATCH 3–STATE 4–BIT LATCH 3–STATE 4–BIT LATCH 4–LINE DATA BUS MC 14508B 3–STATE 4–BIT LATCH 4–LINE DATA BUS MC14519B A B DATA BUS 3–STATE 4–BIT LATCH 14508B MC |
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