MOTOROLA CMOS LOGIC DATA

5

MC14597B MC14598B

MC14598B FUNCTION DIAGRAM

ENABLE

4

RESET

2

STROBE

6

DATA

3

TO OTHER

LATCHES

VDD

VSS

EACH LATCH

ZERO

SELECT

1

D0

17

D1

16

D2

15

D3

14

D4

13

D5

12

D6

11

D7

ADDRESS

DECODER

ADDITIONAL 7 LATCHES

A0

7

A1

8

A2

10

TO OTHER

LATCHES

(M.S.B)

MC14598B TIMING DIAGRAM

* 1.4 V with VDD = 5.0 V

NOTES:

1. High–impedance output state (another device controls bus).

2. Output Load as for MC14597B.

D7

RESET

A0, A1, A2

DATA

STROBE

ENABLE

90%

10%

50%

50%

tPHL

tPLH

1

tTHL

tPLH

90%

10%

tTLH

tW

50%

20 ns

90%

10%

tsu th

th

tsu

90%

10%

50%

90%

10%

20 ns

tW

20 ns

tW

*