ADS7039-Q1 datasheet(5/32 Pages) TI1

Numer części	ADS7039-Q1

Szczegółowy opis	Small-Size, Low-Power, 10-Bit, 2-MSPS, SAR ADC

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Producent	TI1 [Texas Instruments]

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ADS7039-Q1

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SBAS788 – JANUARY 2017

Product Folder Links: ADS7039-Q1

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(1)

Ideal input span; does not include gain or offset error.

(2)

LSB means least significant bit.

(3)

See the Offset Calibration section for more details.

(4)

All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale,

unless otherwise specified.

(5)

Calculated on the first nine harmonics of the input frequency.

(6)

Digital voltage levels comply with the JESD8-7A standard for DVDD from 1.65 V to 1.95 V; see the Digital Voltage Levels section for

more details.

6.5 Electrical Characteristics

at TA = –40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, fSAMPLE = 2 MSPS, and VAINM = 0 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG INPUT

Full-scale input voltage span(1)

0

AVDD

V

Absolute input

voltage range

AINP to GND

–0.1

AVDD + 0.1

V

AINM to GND

–0.1

0.1

CS

Sampling capacitance

15

pF

SYSTEM PERFORMANCE

Resolution

10

Bits

NMC

No missing codes

10

Bits

INL

Integral nonlinearity

AVDD = 3 V

–0.8

±0.4

0.8

LSB(2)

DNL

Differential nonlinearity

AVDD = 3 V

–0.7

±0.4

0.7

LSB

EO

Offset error

Uncalibrated

±3

LSB

Calibrated(3)

AVDD = 3 V

–2

±0.5

2

dVOS/dT

Offset error drift with temperature

±10

ppm/°C

EG

Gain error

AVDD = 3 V

–0.2

±0.1

0.2

%FS

Gain error drift with temperature

No calibration

±10

ppm/°C

SAMPLING DYNAMICS

tACQ

Acquisition time

120

ns

Maximum throughput rate

32-MHz SCLK, AVDD = 2.35 V to 3.6 V

2

MHz

DYNAMIC CHARACTERISTICS

SNR

Signal-to-noise ratio(4)

fIN = 2 kHz, AVDD = 3 V

60

61

dB

THD

Total harmonic distortion(4)(5)

fIN = 2 kHz, AVDD = 3 V

–75

dB

SINAD

Signal-to-noise and distortion(4)

fIN = 2 kHz, AVDD = 3 V

60

61

dB

SFDR

Spurious-free dynamic range(4)

fIN = 2 kHz, AVDD = 3 V

80

dB

BW(fp)

Full-power bandwidth

At –3 dB, AVDD = 3 V

25

MHz

DIGITAL INPUT/OUTPUT (CMOS Logic Family)

VIH

High-level input voltage(6)

0.65 × DVDD

DVDD + 0.3

V

VIL

Low-level input voltage(6)

–0.3

0.35 × DVDD

V

VOH

High-level output voltage(6)

At Isource = 500 µA

0.8 × DVDD

DVDD

V

At Isource = 2 mA

DVDD – 0.45

DVDD

VOL

Low-level output voltage(6)

At Isink = 500 µA

0

0.2 × DVDD

V

At Isink = 2 mA

0

0.45

POWER-SUPPLY REQUIREMENTS

AVDD

Analog supply voltage

2.35

3

3.6

V

DVDD

Digital I/O supply voltage

1.65

3

3.6

V

IAVDD

Analog supply current

At 2 MSPS with AVDD = 3 V

365

400

µA

IDVDD

Digital supply current

AVDD = 3 V, no load, no transitions

10

µA

PD

Power dissipation

At 2 MSPS with AVDD = 3 V

1.095

1.20

mW

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