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AD9164BBCA Arkusz danych(PDF) 5 Page - Analog Devices |
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AD9164BBCA Arkusz danych(HTML) 5 Page - Analog Devices |
5 / 137 page AD9164 Data Sheet Rev. A | Page 4 of 136 SPECIFICATIONS DC SPECIFICATIONS VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 = DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, DAC output full-scale current (IOUTFS) = 40 mA, and TA = −40°C to +85°C, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit RESOLUTION 16 Bit DAC Update Rate Minimum 1.5 GSPS Maximum VDDx1 = 1.3 V ± 2%2 6 6.4 GSPS VDDx1 = 1.3 V ± 2%2, FIR853 2× interpolator enabled 12 12.8 GSPS Adjusted4 VDDx1 = 1.3 V ± 2%2 6 6.4 GSPS ACCURACY Integral Nonlinearity (INL) ±2.7 LSB Differential Nonlinearity (DNL) ±1.7 LSB ANALOG OUTPUTS Gain Error (with Internal Reference) −1.7 % Full-Scale Output Current Minimum RSET = 9.76 kΩ 7.37 8 8.57 mA Maximum RSET = 9.76 kΩ 35.8 38.76 41.3 mA DAC CLOCK INPUT (CLK+, CLK−) Differential Input Power RLOAD = 90 Ω differential on-chip −20 0 +10 dBm Common-Mode Voltage AC-coupled 0.6 V Input Impedance1 3 GSPS input clock 90 Ω TEMPERATURE DRIFT Gain 105 ppm/°C Reference Voltage 75 ppm/°C TEMPERATURE SENSOR Accuracy After single point calibration (See the Temperature Sensor section) ±5 % REFERENCE Internal Reference Voltage 1.19 V ANALOG SUPPLY VOLTAGES VDD25_DAC 2.375 2.5 2.625 V VDD12A2 1.14 1.2 1.326 V VDD12_CLK2 1.14 1.2 1.326 V VNEG_N1P2 −1.26 −1.2 −1.14 V DIGITAL SUPPLY VOLTAGES DVDD Includes VDD12_DCD/DLL 1.14 1.2 1.326 V IOVDD3 1.71 2.5 3.465 V SERDES SUPPLY VOLTAGES VDD_1P2 1.14 1.2 1.326 V VTT_1P2 Can connect to VDD_1P2 1.14 1.2 1.326 V DVDD_1P2 1.14 1.2 1.326 V PLL_LDO_VDD12 1.14 1.2 1.326 V PLL_CLK_VDD12 Can connect to PLL_LDO_VDD12 1.14 1.2 1.326 V SYNC_VDD_3P3 3.135 3.3 3.465 V BIAS_VDD_1P2 Can connect to VDD_1P2 1.14 1.2 1.326 V 1 See the Clock Input section for more details. 2 For the lowest noise performance, use a separate power supply filter network for the VDD12_CLK and the VDD12A pins. 3 IOVDD can range from 1.8 V to 3.3 V, with ±5% tolerance. 4 The adjusted DAC update rate is calculated as fDAC divided by the minimum required interpolation factor. For the AD9164, the minimum interpolation factor is 1. Therefore, with fDAC = 6 GSPS, fDAC adjusted = 6 GSPS. When FIR85 is enabled, which puts the device into 2× NRZ mode, fDAC = 2 × (DAC clock input frequency), and the minimum interpolation increases to 2× (interpolation value). Thus, for the AD9164, with FIR85 enabled and DAC clock = 6 GSPS, fDAC = 12 GSPS, minimum interpolation = 2×, and the adjusted DAC update rate = 6 GSPS. |
Podobny numer części - AD9164BBCA |
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Podobny opis - AD9164BBCA |
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