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ADSP-BF700 Arkusz danych(PDF) 11 Page - Analog Devices |
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ADSP-BF700 Arkusz danych(HTML) 11 Page - Analog Devices |
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11 / 116 page  Rev. A | Page 11 of 116 | September 2015 ADSP-BF700/701/702/703/704/705/706/707 Serial Peripheral Interface (SPI) Ports The processors have three industry-standard SPI-compatible ports that allow it to communicate with multiple SPI-compati- ble devices. The baseline SPI peripheral is a synchronous, four-wire inter- face consisting of two data pins, one device select pin, and a gated clock pin. The two data pins allow full-duplex operation to other SPI-compatible devices. An additional two (optional) data pins are provided to support quad SPI operation. Enhanced modes of operation such as flow control, fast mode, and dual I/O mode (DIOM) are also supported. In addition, a direct memory access (DMA) mode allows for transferring several words with minimal CPU interaction. With a range of configurable options, the SPI ports provide a glueless hardware interface with other SPI-compatible devices in master mode, slave mode, and multimaster environments. The SPI peripheral includes programmable baud rates, clock phase, and clock polarity. The peripheral can operate in a multi- master environment by interfacing with several other devices, acting as either a master device or a slave device. In a multimas- ter environment, the SPI peripheral uses open-drain outputs to avoid data bus contention. The flow control features enable slow slave devices to interface with fast master devices by providing an SPI Ready pin which flexibly controls the transfers. The SPI port’s baud rate and clock phase/polarities are pro- grammable, and it has integrated DMA channels for both transmit and receive data streams. SPI Host Port (SPIHP) The processor includes one SPI host port which may be used in conjunction with any available SPI port to enhance its SPI slave mode capabilities. The SPIHP allows a SPI host device access to memory-mapped resources of the processor through a SPI SRAM/FLASH style protocol. The following features are included: • Direct read/write of memory and memory-mapped registers • Support for pre-fetch for faster reads • Support for SPI controllers that implement hardware- based SPI memory protocol • Error capture and reporting for protocol errors, bus errors, and over/underflow UART Ports The processor provides two full-duplex universal asynchronous receiver/transmitter (UART) ports, which are fully compatible with PC-standard UARTs. Each UART port provides a simpli- fied UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. A UART port includes support for five to eight data bits, and none, even, or odd parity. Optionally, an additional address bit can be transferred to interrupt only addressed nodes in multi-drop bus (MDB) systems. A frame is terminated by a con- figurable number of stop bits. The UART ports support automatic hardware flow control through the clear to send (CTS) input and request to send (RTS) output with programmable assertion FIFO levels. To help support the local interconnect network (LIN) protocols, a special command causes the transmitter to queue a break command of programmable bit length into the transmit buffer. Similarly, the number of stop bits can be extended by a pro- grammable inter-frame space. The capabilities of the UARTs are further extended with sup- port for the Infrared Data Association (IrDA®) serial infrared physical layer link specification (SIR) protocol. 2-Wire Controller Interface (TWI) The processor includes a 2-wire interface (TWI) module for providing a simple exchange method of control data between multiple devices. The TWI module is compatible with the widely used I2C bus standard. The TWI module offers the capabilities of simultaneous master and slave operation and support for both 7-bit addressing and multimedia data arbitra- tion. The TWI interface utilizes two pins for transferring clock (TWI_SCL) and data (TWI_SDA) and supports the protocol at speeds up to 400k bits/sec. The TWI interface pins are compati- ble with 5 V logic levels. Additionally, the TWI module is fully compatible with serial camera control bus (SCCB) functionality for easier control of various CMOS camera sensor devices. Mobile Storage Interface (MSI) The mobile storage interface (MSI) controller acts as the host interface for multimedia cards (MMC), secure digital memory cards (SD), and secure digital input/output cards (SDIO). The following list describes the main features of the MSI controller: • Support for a single MMC, SD memory, and SDIO card • Support for 1-bit and 4-bit SD modes • Support for 1-bit, 4-bit, and 8-bit MMC modes • Support for eMMC 4.5 embedded NAND flash devices • Support for power management and clock control • An eleven-signal external interface with clock, command, optional interrupt, and up to eight data lines • Card interface clock generation from SCLK0 or SCLK1 • SDIO interrupt and read wait features Controller Area Network (CAN) A CAN controller implements the CAN 2.0B (active) protocol. This protocol is an asynchronous communications protocol used in both industrial and automotive control systems. The CAN protocol is well suited for control applications due to its capability to communicate reliably over a network. This is because the protocol incorporates CRC checking, message error tracking, and fault node confinement. |
Podobny numer części - ADSP-BF700 |
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Podobny opis - ADSP-BF700 |
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