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ADSP-BF700KCPZ-1 Arkusz danych(PDF) 5 Page - Analog Devices |
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ADSP-BF700KCPZ-1 Arkusz danych(HTML) 5 Page - Analog Devices |
5 / 116 page Rev. A | Page 5 of 116 | September 2015 ADSP-BF700/701/702/703/704/705/706/707 The program sequencer controls the flow of instruction execu- tion, including instruction alignment and decoding. For program flow control, the sequencer supports PC relative and indirect conditional jumps (with dynamic branch prediction), and subroutine calls. Hardware supports zero-overhead loop- ing. The architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies. The address arithmetic unit provides two addresses for simulta- neous dual fetches from memory. It contains a multiported register file consisting of four sets of 32-bit index, modify, length, and base registers (for circular buffering), and eight additional 32-bit pointer registers (for C-style indexed stack manipulation). The Blackfin processor supports a modified Harvard architec- ture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full pro- cessor speed with little or no latency. At the L1 level, the instruction memory holds instructions only. The data memory holds data, and a dedicated scratchpad data memory stores stack and local variable information. In addition, multiple L1 memory blocks are provided, offering a configurable mix of SRAM and cache. The memory manage- ment unit (MMU) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access. The architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources. INSTRUCTION SET DESCRIPTION The Blackfin processor instruction set has been optimized so that 16-bit opcodes represent the most frequently used instruc- tions, resulting in excellent compiled code density. Complex DSP instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. The Blackfin proces- sor supports a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instruc- tions, allowing the programmer to use many of the core resources in a single instruction cycle. The Blackfin processor family assembly language instruction set employs an algebraic syntax designed for ease of coding and readability. The instructions have been specifically tuned to pro- vide a flexible, densely encoded instruction set that compiles to a very small final memory size. The instruction set also provides fully featured multifunction instructions that allow the pro- grammer to use many of the processor core resources in a single instruction. Coupled with many features more often seen on microcontrollers, this instruction set is very efficient when com- piling C and C++ source code. In addition, the architecture supports both user (algorithm/application code) and supervisor (O/S kernel, device drivers, debuggers, ISRs) modes of opera- tion, allowing multiple levels of access to core processor resources. The assembly language, which takes advantage of the proces- sor’s unique architecture, offers the following advantages: • Seamlessly integrated DSP/MCU features are optimized for both 8-bit and 16-bit operations. • A multi-issue load/store modified-Harvard architecture, which supports two 16-bit MAC or four 8-bit ALU + two load/store + two pointer updates per cycle. • All registers, I/O, and memory are mapped into a unified 4G byte memory space, providing a simplified program- ming model. • Control of all asynchronous and synchronous events to the processor is handled by two subsystems: the core event controller (CEC) and the system event controller (SEC). • Microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data-types; and separate user and supervisor stack pointers. • Code density enhancements, which include intermixing of 16-bit and 32-bit instructions (no mode switching, no code segregation). Frequently used instructions are encoded in 16 bits. PROCESSOR INFRASTRUCTURE The following sections provide information on the primary infrastructure components of the ADSP-BF70x processor. DMA Controllers The processor uses direct memory access (DMA) to transfer data within memory spaces or between a memory space and a peripheral. The processor can specify data transfer operations and return to normal processing while the fully integrated DMA controller carries out the data transfers independent of proces- sor activity. DMA transfers can occur between memory and a peripheral or between one memory and another memory. Each memory-to- memory DMA stream uses two channels, where one channel is the source channel, and the second is the destination channel. All DMAs can transport data to and from all on-chip and off- chip memories. Programs can use two types of DMA transfers, descriptor-based or register-based. Register-based DMA allows the processor to directly program DMA control registers to ini- tiate a DMA transfer. On completion, the control registers may be automatically updated with their original setup values for continuous transfer. Descriptor-based DMA transfers require a set of parameters stored within memory to initiate a DMA sequence. Descriptor-based DMA transfers allow multiple DMA sequences to be chained together and a DMA channel can be programmed to automatically set up and start another DMA transfer after the current sequence completes. The DMA controller supports the following DMA operations. • A single linear buffer that stops on completion. • A linear buffer with negative, positive, or zero stride length. • A circular, auto-refreshing buffer that interrupts when each buffer becomes full. |
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Podobny opis - ADSP-BF700KCPZ-1 |
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