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ADSP-BF703KBCZ-3 Arkusz danych(PDF) 6 Page - Analog Devices |
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ADSP-BF703KBCZ-3 Arkusz danych(HTML) 6 Page - Analog Devices |
6 / 116 page Rev. A | Page 6 of 116 | September 2015 ADSP-BF700/701/702/703/704/705/706/707 • A similar buffer that interrupts on fractional buffers (for example, 1/2, 1/4). • 1D DMA—uses a set of identical ping-pong buffers defined by a linked ring of two-word descriptor sets, each contain- ing a link pointer and an address. • 1D DMA—uses a linked list of 4 word descriptor sets con- taining a link pointer, an address, a length, and a configuration. • 2D DMA—uses an array of one-word descriptor sets, spec- ifying only the base DMA address. • 2D DMA—uses a linked list of multi-word descriptor sets, specifying everything. Event Handling The processor provides event handling that supports both nest- ing and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher-priority event takes precedence over ser- vicing of a lower-priority event. The processor provides support for five different types of events: • Emulation—An emulation event causes the processor to enter emulation mode, allowing command and control of the processor through the JTAG interface. • Reset—This event resets the processor. • Nonmaskable interrupt (NMI)—The NMI event can be generated either by the software watchdog timer, by the NMI input signal to the processor, or by software. The NMI event is frequently used as a power-down indicator to initiate an orderly shutdown of the system. • Exceptions—Events that occur synchronously to program flow (in other words, the exception is taken before the instruction is allowed to complete). Conditions such as data alignment violations and undefined instructions cause exceptions. • Interrupts —Events that occur asynchronously to program flow. They are caused by input signals, timers, and other peripherals, as well as by an explicit software instruction. System Event Controller (SEC) The SEC manages the enabling, prioritization, and routing of events from each system interrupt or fault source. Additionally, it provides notification and identification of the highest priority active system interrupt request to the core and routes system fault sources to its integrated fault management unit. The SEC triggers core general-purpose interrupt IVG11. It is recom- mended that IVG11 be set to allow self-nesting. The four lower priority interrupts (IVG15-12) may be used for software interrupts. Trigger Routing Unit (TRU) The TRU provides system-level sequence control without core intervention. The TRU maps trigger masters (generators of trig- gers) to trigger slaves (receivers of triggers). Slave endpoints can be configured to respond to triggers in various ways. Common applications enabled by the TRU include: • Automatically triggering the start of a DMA sequence after a sequence from another DMA channel completes • Software triggering • Synchronization of concurrent activities General-Purpose I/O (GPIO) Each general-purpose port pin can be individually controlled by manipulation of the port control, status, and interrupt registers: • GPIO direction control register—Specifies the direction of each individual GPIO pin as input or output. • GPIO control and status registers—A write one to modify mechanism allows any combination of individual GPIO pins to be modified in a single instruction, without affect- ing the level of any other GPIO pins. • GPIO interrupt mask registers—Allow each individual GPIO pin to function as an interrupt to the processor. GPIO pins defined as inputs can be configured to generate hardware interrupts, while output pins can be triggered by software interrupts. • GPIO interrupt sensitivity registers—Specify whether indi- vidual pins are level- or edge-sensitive and specify—if edge-sensitive—whether just the rising edge or both the ris- ing and falling edges of the signal are significant. Pin Interrupts Every port pin on the processor can request interrupts in either an edge-sensitive or a level-sensitive manner with programma- ble polarity. Interrupt functionality is decoupled from GPIO operation. Three system-level interrupt channels (PINT0–3) are reserved for this purpose. Each of these interrupt channels can manage up to 32 interrupt pins. The assignment from pin to interrupt is not performed on a pin-by-pin basis. Rather, groups of eight pins (half ports) can be flexibly assigned to interrupt channels. Every pin interrupt channel features a special set of 32-bit mem- ory-mapped registers that enable half-port assignment and interrupt management. This includes masking, identification, and clearing of requests. These registers also enable access to the respective pin states and use of the interrupt latches, regardless of whether the interrupt is masked or not. Most control registers feature multiple MMR address entries to write-one-to-set or write-one-to-clear them individually. Pin Multiplexing The processor supports a flexible multiplexing scheme that mul- tiplexes the GPIO pins with various peripherals. A maximum of 4 peripherals plus GPIO functionality is shared by each GPIO pin. All GPIO pins have a bypass path feature—that is, when the |
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