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AD9144BCPZRL Arkusz danych(PDF) 10 Page - Analog Devices |
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AD9144BCPZRL Arkusz danych(HTML) 10 Page - Analog Devices |
10 / 126 page Data Sheet AD9144 Rev. A | Page 9 of 125 LATENCY VARIATION SPECIFICATIONS AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V, TA = 25°C, IOUTFS = 20 mA, unless otherwise noted. Table 7. Parameter Min Typ Max Unit DAC LATENCY VARIATION SYNC On PLL Off 0 1 DACCLK cycles PLL On −1 +1 DACCLK cycles JESD204B INTERFACE ELECTRICAL SPECIFICATIONS AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V, TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted. Table 8. Parameter Symbol Test Conditions/Comments Min Typ Max Unit JESD204B DATA INPUTS Input Leakage Current 25°C Logic High Input level = 1.2 V ± 0.25 V, VTT = 1.2 V 10 μA Logic Low Input level = 0 V −4 μA Unit Interval UI 94 714 ps Common-Mode Voltage VRCM AC-coupled, VTT = SVDD121 −0.05 +1.85 V Differential Voltage R_VDIFF 110 1050 mV VTT Source Impedance ZTT At dc 30 Ω Differential Impedance ZRDIFF At dc 80 100 120 Ω Differential Return Loss RLRDIF 8 dB Common-Mode Return Loss RLRCM 6 dB DIFFERENTIAL OUTPUTS (SYNCOUT±)2 Output Differential Voltage VOD Normal swing mode: Register 0x2A5[0] = 0 192 235 mV Output Offset Voltage VOS 1.19 1.27 V Output Differential Voltage VOD High swing mode: Register 0x2A5[0] = 1 341 394 mV DETERMINISTIC LATENCY Fixed 17 PClock3 cycles Variable 2 PClock3 cycles SYSREF±-to-LMFC DELAY 4 DAC clock cycles 1 As measured on the input side of the ac coupling capacitor. 2 IEEE Standard 1596.3 LVDS compatible. 3 PClock is the AD9144 internal processing clock and equals the lane rate ÷ 40. |
Podobny numer części - AD9144BCPZRL |
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Podobny opis - AD9144BCPZRL |
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