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AD9144-M6720-EBZ Arkusz danych(PDF) 9 Page - Analog Devices

Numer części AD9144-M6720-EBZ
Szczegółowy opis  Multiple chip synchronization
Download  126 Pages
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

AD9144-M6720-EBZ Arkusz danych(HTML) 9 Page - Analog Devices

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AD9144
Data Sheet
Rev. A | Page 8 of 125
SYSREF TO DAC CLOCK TIMING SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = −40°C to +85°C, IOUTFS = 20 mA, SYSREF± common-mode voltages = 0.0 V, 0.6 V, 1.25 V, and 2.0 V, unless otherwise noted.
Table 5.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
SYSREF DIFFERENTIAL SWING = 0.4 V, SLEW RATE = 1.3 V/ns
Setup Time
AC-coupled
126
ps
DC-coupled
131
ps
Hold Time
AC-coupled
92
ps
DC-coupled
119
ps
SYSREF DIFFERENTIAL SWING = 0.7 V, SLEW RATE = 2.28 V/ns
Setup Time
AC-coupled
96
ps
DC-coupled
104
ps
Hold Time
AC-coupled
77
ps
DC-coupled
95
ps
SYSREF SWING = 1.0 V, SLEW RATE = 3.26 V/ns
Setup Time
AC-coupled
83
ps
DC-coupled
90
ps
Hold Time
AC-coupled
68
ps
DC-coupled
84
ps
DIGITAL INPUT DATA TIMING SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = 25°C, IOUTFS = 20 mA, unless otherwise noted.
Table 6.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
LATENCY
Interface
17
PClock1 cycles
Interpolation
58
DAC clock cycles
137
DAC clock cycles
251
DAC clock cycles
484
DAC clock cycles
Inverse Sinc
17
DAC clock cycles
Fine Modulation
20
DAC clock cycles
Coarse Modulation
fS/8
8
DAC clock cycles
fS/4
4
DAC clock cycles
Digital Phase Adjust
12
DAC clock cycles
Digital Gain Adjust
12
DAC clock cycles
Power-Up Time
Dual A Only
Register 0x011 from 0x60 to 0x00
60
μs
Dual B Only
Register 0x011 from 0x18 to 0x00
60
μs
All DACs
Register 0x011 from 0x7C to 0x00
60
μs
1 PClock is the AD9144 internal processing clock and equals the lane rate ÷ 40.


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