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ADP5053-EVALZ Arkusz danych(PDF) 10 Page - Analog Devices

Numer części ADP5053-EVALZ
Szczegółowy opis  Integrated Power Solution with Quad Buck
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ADP5053-EVALZ Arkusz danych(HTML) 10 Page - Analog Devices

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Data Sheet
ADP5053
Rev. B | Page 9 of 36
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
PVIN1
PVIN1
SW1
4
SW1
5
BST1
6
DL1
7
PGND
TOP VIEW
(Not to Scale)
ADP5053
25
BST4
26
PGND4
27
SW4
28
PVIN4
29
30
31
VTH
32
WDI
33
PVIN3
34
SW3
35
PGND3
36
BST3
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED AND
SOLDERED TO AN EXTERNAL GROUND PLANE.
8
DL2
9
BST2
10
SW2
11
SW2
12
PVIN2
MR
RSTO
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
BST3
High-Side FET Driver Power Supply for Channel 3.
2
PGND3
Power Ground for Channel 3.
3
SW3
Switching Node Output for Channel 3.
4
PVIN3
Power Input for Channel 3. Connect a bypass capacitor between this pin and ground.
5
WDI
Watchdog Refresh Input from Processor.
6
VTH
Monitoring Voltage Threshold Programming.
7
MR
Manual Reset Input, Active Low.
8
RSTO
Open-Drain Reset Output, Active Low.
9
PVIN4
Power Input for Channel 4. Connect a bypass capacitor between this pin and ground.
10
SW4
Switching Node Output for Channel 4.
11
PGND4
Power Ground for Channel 4.
12
BST4
High-Side FET Driver Power Supply for Channel 4.
13
GND
This pin is for internal test purposes. Connect this pin to ground.
14
EN4
Enable Input for Channel 4. Use an external resistor divider to set the turn-on threshold.
15
COMP4
Error Amplifier Output for Channel 4. Connect an RC network from this pin to ground.
16
FB4
Feedback Sensing Input for Channel 4.
17, 18, 19
GND
These pins are for internal test purposes. Connect these pins to ground.
20
PWRGD
Power-Good Signal Output. This open-drain output is the power-good signal for the selected channels.
21
FB2
Feedback Sensing Input for Channel 2.
22
COMP2
Error Amplifier Output for Channel 2. Connect an RC network from this pin to ground.
23
EN2
Enable Input for Channel 2. Use an external resistor divider to set the turn-on threshold.
24, 25
PVIN2
Power Input for Channel 2. Connect a bypass capacitor between this pin and ground.
26, 27
SW2
Switching Node Output for Channel 2.
28
BST2
High-Side FET Driver Power Supply for Channel 2.
29
DL2
Low-Side FET Gate Driver for Channel 2. Connect a resistor from this pin to ground to program the current-
limit threshold for Channel 2.
30
PGND
Power Ground for Channel 1 and Channel 2.
31
DL1
Low-Side FET Gate Driver for Channel 1. Connect a resistor from this pin to ground to program the current-
limit threshold for Channel 1.


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