SN74CB3Q3345

8BIT FET BUS SWITCH

2.5V/3.3V LOW VOLTAGE HIGHBANDWIDTH BUS SWITCH

SCDS144A − OCTOBER 2003 − REVISED NOVEMBER 2003

2

POST OFFICE BOX 655303

description/ordering information

The SN74CB3Q3345 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage

allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The

device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data

bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q3345 provides an optimized

interface solution ideally suited for broadband communications, networking, and data-intensive computing

systems.

The SN74CB3Q3384A is organized as an 8-bit bus switch with two output-enable (OE, OE) inputs. When OE

is high or OE is low, the bus switch is ON, and the A port is connected to the B port, allowing bidirectional data

flow between ports. When OE is low and OE is high, the bus switch is OFF, and a high-impedance state exists

between the A and B ports.

current backflow through the device when it is powered down. The device has isolation during power off.

resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is

determined by the current-sinking/current-sourcing capability of the driver.

ORDERING INFORMATION

TA

PACKAGE†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

QFN − RGY

Tape and reel

SN74CB3Q3345RGYR

BU345

SSOP (QSOP) − DBQ

Tape and reel

SN74CB3Q3345DBQR

CB3Q3345

−40

°C to 85°C

TSSOP − PW

Tube

SN74CB3Q3345PW

BU345

−40 C to 85 C

TSSOP − PW

Tape and reel

SN74CB3Q3345PWR

BU345

TVSOP − DGV

Tape and reel

SN74CB3Q3345DGVR

BU345

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

FUNCTION TABLE

INPUTS

INPUT/OUTPUT

FUNCTION

OE

OE

INPUT/OUTPUT

A

FUNCTION

H

X

B

A port = B port

X

L

B

A port = B port

L

H

Z

Disconnect

logic diagram (positive logic)

A1

A8

OE

B1

B8

OE

2

9

1

19

18

11

SW

SW