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TPL5110QDDCTQ1 Arkusz danych(PDF) 6 Page - Texas Instruments |
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TPL5110QDDCTQ1 Arkusz danych(HTML) 6 Page - Texas Instruments |
6 / 27 page 6 TPL5110-Q1 SNAS681 – FEBRUARY 2017 www.ti.com Product Folder Links: TPL5110-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) Electrical Characteristics Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. (2) Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through correlations using statistical quality control (SQC) method. (3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped production material. (4) The supply current excludes load and pull-up resistor current. Input pins are at GND or VDD. (5) This parameter is specified by design and/or characterization and is not tested in production. (6) The accuracy for time interval settings below 1second is ±100ms. (7) Operational life time test procedure equivalent to10 years. 7.5 Electrical Characteristics (1) Specifications are for TA= 25°C, VDD-GND=2.5 V, unless otherwise stated. PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT POWER SUPPLY IDD Supply current(4) Operation mode 35 50 nA Digital conversion of external resistance (Rext) 200 400 µA TIMER tIP Time interval Period(5) 1650 selectable Time intervals Min time interval 100 ms Max time interval 7200 s Time interval Setting Accuracy(6) Excluding the precision of Rext ±0.6% Time interval Setting Accuracy over supply voltage 1.8V ≤ VDD ≤ 5.5V ±25 ppm/V tOSC Oscillator Accuracy –0.5% 0.5% Oscillator Accuracy over temperature(5) –40°C ≤ TA≤ 125°C 150 ppm/°C Oscillator Accuracy over supply voltage(5) 1.8V ≤ VDD ≤ 5.5V ±0.4 %/V Oscillator Accuracy over life time(7) ±0.24% tDONE Minimum DONE Pulse width (5) 100 ns tDRV DRV Pulse width DONE signal not received tIP–50ms t_Rext Time to convert Rext (5) 100 ms DIGITAL LOGIC LEVELS VIH Minimum Logic High Threshold DONE pin 0.7xVDD V VIL Maximum Logic Low Threshold DONE pin 0.3xVDD V VOH Logic output High Level DRV pin Iout = 100 µA VDD–0.3 V Iout = 1 mA VDD–0.7 V VOL Logic output Low Level DRV pin Iout = –100 µA 0.3 V Iout = –1 mA 0.7 V VIHM_DRV Minimum Logic High Threshold DELAY/M_DRV pin (5) 1.5 V |
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