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ADC700 Arkusz danych(PDF) 10 Page - Burr-Brown (TI) |
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ADC700 Arkusz danych(HTML) 10 Page - Burr-Brown (TI) |
10 / 12 page 10 ® ADC700 –10V to +10V Range—Set the analog input to –FS + 1LSB 14 = –9.99878V. Adjust the Offset potentiometer for a digital output of 0004H (8004H if BTCEN is asserted). Set the analog input to +9.9976V. Adjust the Gain potentiometer for a digital output of FFFCH (7FFCH if BTCEN is assrted). For a half-scale calibration check, set the analog input to 0.0000V and read a digital output code of 8000H (0000H if BTCEN is asserted). CONTROLLING AND INTERFACING THE ADC700 RESET The ADC700 requires a Reset command upon power-up or after a power interruption to guarantee the condition of internal registers. If Status powers-up High, no conversion can be started. Reset initializes the SAR, the output buffer register, and the Data Ready flag and terminates a conver- sion in progress. Since microprocessor systems already use a power-on reset circuit, the same system reset signal can be used to initialize the ADC700. A power-up circuit is shown in Figure 8. Refer to Reset function timing diagram follow- ing the Timing Specifications Table. START OF CONVERSION A conversion is started by asserting CS and WR Low. Status goes high about t = t1 + t2 = 110ns later. The first successive approximation decision occurs about 900ns after WR is asserted. Status goes Low after the conversion is complete. Refer to Start of Conversion and Serial Data Output Timing following the Timing Specifications Table. DATA READY FLAG The data latch feature permits data to be read during the following conversion. The Data Ready flag indicates that the data from the most recent conversion is latched in the output data latch and that it hasn’t been read. Data Ready remains High until the most significant data byte is read. If a subsequent conversion is initiated and completed, the new word will be stored in the output data latch regardless of the state of the Data Ready flag. The preceding word will be overwritten and lost. READING PARALLEL DATA Parallel data is latched in the output data latch at the end of a conversion. Data can be read any time, even during the subsequent conversion. The output data latch is not cleared by reading the data. Only the Data Ready flag is cleared by reading the MSB. The output three-state drivers are enabled by asserting the CS and RD inputs Low. When HBEN is Low, the most significant eight bits are enabled and the Data Ready flag is cleared. When HBEN is High, the least significant eight bits are enabled. Refer to Parallel Data Output Timing informa- tion following the Timing Specifications Table. To reduce noise interference to the absolute minimum, data should be read after the current conversion is complete. However, data can be read during the following conversion, with minimal interference, to maximize the sampling rate of the converter. A typical parallel interface is illustrated in Figure 9. READING SERIAL DATA Serial data output of the ADC700 is facilitated by a Serial Data Strobe that provides 16 negative-going edges for strobing an external serial to parallel shift register located perhaps on the other side of an opto-coupler. Refer to the Serial Data Timing information following the Timing Specifications Table. An example of an isolation connection using the serial port feature is illustrated in Figure 10. CONTINUOUS CONVERSION OPERATION When CS is permanently connected to Digital Common and Status is connected to WR, Figure 11, the ADC700 will continuously convert. The repetition time will not be precise and will vary slightly with the temperature for the ADC700 because the time will be determined by the internal clock frequency and control-circuit gate delays. If a precise repe- tition rate is needed, the continuous conversion connection should not be used. FIGURE 8. Power-Up Reset Circuit. ADC700 V DD Reset +5V 50k Ω 100pF 24 6 FIGURE 9. Parallel Data Bus Interface. Microprocessor ADC700 A 0–AXX Address Decoder CS WR RD Data Ready Reset DB 0–DB7 WR RD INT Reset DB 0–DB7 System Reset |
Podobny numer części - ADC700 |
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Podobny opis - ADC700 |
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