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ADC700SH Arkusz danych(PDF) 3 Page - Burr-Brown (TI) |
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ADC700SH Arkusz danych(HTML) 3 Page - Burr-Brown (TI) |
3 / 12 page 3 ® ADC700 *Same specs as ADC700JH, AH, RH. ORDERING INFORMATION TEMPERATURE LINEARITY MODEL RANGE ERROR (%FSR) 1–24 25–99 100+ ADC700JH 0 °C to 70°C ±0.006 ADC700KH 0 °C to 70°C ±0.003 ADC700AH –25 °C to +85°C ±0.006 ADC700BH –25 °C to +85°C ±0.003 ADC700RH –55 °C to +125°C ±0.006 ADC700SH –55 °C to +125°C ±0.003 ABSOLUTE MAXIMUM RATINGS +VDD to Digital Common ............................................................ 0V to +7V +VCC to Analog Common ......................................................... 0V to +18V –VCC to Analog Common ......................................................... 0V to –18V Digital Common to Analog Common ........................................ –1V to +1V Digital Inputs to Digital Common ................................ –0.5V to VDD + 0.5V Analog Inputs .................................................................................. +16.5V Power Dissipation ........................................................................ 1000mW Storage Temperature ...................................................... –60 °C to +150°C Lead Temperature, (soldering, 10s) ............................................... +300 °C NOTES: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maxi- mum rating conditions for extended periods may affect device reliability. PACKAGING INFORMATION PACKAGE DRAWING MODEL PACKAGE NUMBER(1) ADC700JH 28-Pin Ceramic DIP 237 ADC700KH 28-Pin Ceramic DIP 237 ADC700AH 28-Pin Ceramic DIP 237 ADC700BH 28-Pin Ceramic DIP 237 ADC700RH 28-Pin Ceramic DIP 237 ADC700SH 28-Pin Ceramic DIP 237 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. LIMIT AT LIMIT AT TA = 0, +70°C LIMIT AT PARAMETER TA = 25°C –25 °C, +85°CT A = –55°C, +125°C UNITS DESCRIPTION CONVERSION AND SERIAL DATA OUTPUT TIMING t1 0 0 0 ns, min CS to WR Setup time t2 110 130 145 ns, max WR to Status delay t3 40 40 40 ns, min WR pulse width t4 0 0 0 ns, min CS to WR Hold time t5 15 17 17 µs, max Conversion time t6 550 600 650 ns, max Data Ready to Status time t7 1100 1150 1250 ns, max WR to first Serial Data Strobe t8 250 210 200 ns, min First Serial Data to first Serial Data Strobe t9 310 360 400 ns, max Last Serial Data Strobe to Status t10 0 0 0 ns, min Status to WR Setup time PARALLEL DATA OUTPUT TIMING t11 0 0 0 ns, min HBEN to RD Setup time t12 0 0 0 ns, min CS to RD Setup time t13 (7) 50 58 66 ns, max High Byte Data Valid after RD CL = 20pF (High Byte bus access time) 70 81 95 ns, max High Byte Data Valid after RD CL = 100pF (High Byte bus access time) t14 40 40 40 ns, min RD pulse width t15 40 45 50 ns, max Data Ready delay from RD (HBEN asserted) t16(8) 50 60 65 ns, max Data Hold time after RD (bus relinquish time) t17 0 0 0 ns, min RD to CS Hold time t18 0 0 0 ns, min RD to HBEN Hold time RESET TIMING t19 60 70 80 ns, max Data Ready low delay from Reset t20 70 81 95 ns, max Status low delay from Reset NOTES: (1) TTL, LSTTL, and 5V CMOS compatible. (2) FSR means Full Scale Range. For example, unit connected for ±10V range has 20V FSR. (3) Externally adjustable to zero. (4) See Table I. USB – Unipolar Straight Binary; BTC – Binary Two’s Complement; BOB – Bipolar Offset Binary; NRZ – Non Return to Zero. (5) Max supply current is specified at rated supply voltages. (6) All input control signals are specified with tRISE = tFALL = 5ns (10% to 90% of 5V) and timed from a voltage level of 1.6V. (7) t13 is measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V. (8) t16 is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2. TIMING SPECIFICATIONS(6) At VDD = +5V, +VCC = +12V or +15V, –VCC = –12V or –15V, unless otherwise noted. |
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