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ADC10D1000DAISY Arkusz danych(PDF) 7 Page - Texas Instruments

Numer części ADC10D1000DAISY
Szczegółowy opis  12-Bit, Single Or Dual, 3200- or 1600-MSPS RF Sampling Analog-to-Digital Converter (ADC)
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ADC10D1000DAISY Arkusz danych(HTML) 7 Page - Texas Instruments

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GND
VA
GND
VA
GND
VA
50 k:
GND
VA
GND
VA
7
ADC12D1620QML-SP
www.ti.com
SNAS717 – APRIL 2017
Product Folder Links: ADC12D1620QML-SP
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Pin Functions: Analog Front-End and Clock Pins (continued)
PIN
TYPE
DESCRIPTION
EQUIVALENT CIRCUIT
NAME
NO.
DDRPh
W4
I
DDR phase select. In DDR, when this input is logic-
low, it selects the 0° data-to-DCLK phase
relationship. When this input is logic-high, it selects
the 90° data-to-DCLK phase relationship; that is, the
DCLK transition indicates the middle of the valid
data outputs.
In SDR, when this input is logic-low, the output
transitions on the rising edge of DCLK. When this
input is logic-high, output transition is on the falling
edge of DCLK.
This pin only has an effect when the chip is in 1:2
demuxed mode; that is, the NDM pin is set to logic-
low. In ECM, this input is ignored and the DDR
phase is selected through the Control Register by
the DPS bit (Addr: 0h, Bit 14); the default is 0°
mode.
DES
V5
I
Dual edge sampling (DES) mode select. In the non-
extended control mode (Non-ECM), when this input
is set to logic-high, the DES mode of operation is
selected; this means that the VinI input is sampled
by both channels in a time-interleaved manner and
the VinQ input is ignored.
When this input is set to logic-low, the device is in
non-DES mode; that is, I and Q channels operate
independently. In the extended control mode (ECM),
this input is ignored and DES mode selection is
controlled through the DES bit of the Configuration
Register (Addr: 0h; Bit: 7); default is non-DES mode
operation.
ECE
B3
I
Extended control enable. Extended feature control
through the SPI interface is enabled and the device
is in ECM when this signal is asserted (logic-low).
Please reference Table 1 for information on the
behavior of the control pins when the extended
feature control is enabled.
When this signal is de-asserted (logic-high), the SPI
interface is disabled, all SPI registers are reset to
their default values, and all available settings are
controlled with the control pins.
FSR
Y3
I
Full-scale input range select. In non-ECM, when this
input is set to logic-low or logic-high, the full-scale
differential input range for both I- and Q-channel
inputs is set to the lower or higher FSR value,
respectively. In the ECM, this input is ignored and
the full-scale range of the I- and Q-channelinputs is
independently determined by the setting of the I-
and Q-channel Full-Scale Range Adjust Registers
(Addr: 3h and Addr: Bh, respectively). Note that the
high (lower) FSR value in non-ECM corresponds to
the mid (min) available selection in ECM; the FSR
range in ECM is greater.
LSPSM
V4
I
Low-sampling power-saving mode (LSPSM) select.
In LSPSM, the power consumption is reduced by
approximately 20%, and some improvement in
performance may be seen. The output is in SDR in
1:2 demux mode and DDR in 1:1 non-demux mode.
DDR is not available in 1:2 demux mode in LSPSM.
The maximum sampling rate in LSPSM in non-DES
mode is 800 MSPS. When this input is logic-high,
the device is in LSPSM and when this input is logic-
low, the device is in normal mode or non-LSPSM.


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