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CDCV857BIDGGG4 Arkusz danych(PDF) 1 Page - Texas Instruments

Numer części CDCV857BIDGGG4
Szczegółowy opis  2.5-V PHASE-LOCK LOOP CLOCK DRIVER
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Producent  TI1 [Texas Instruments]
Strona internetowa  http://www.ti.com
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CDCV857BIDGGG4 Arkusz danych(HTML) 1 Page - Texas Instruments

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CDCV857B, CDCV857BI
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS689A − FEBRUARY 2003 − REVISED NOVEMBER 2010
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Phase-Lock Loop Clock Driver for Double
Data-Rate Synchronous DRAM
Applications
D Spread Spectrum Clock Compatible
D Operating Frequency: 60 MHz to 200 MHz
D Low Jitter (cycle-cycle): ±50 ps
D Low Static Phase Offset: ±50 ps
D Low Jitter (Period): ±35 ps
D Distributes One Differential Clock Input to
10 Differential Outputs
D Enters Low-Power Mode When No CLK
Input Signal Is Applied or PWRDWN Is Low
D Operates From Dual 2.5-V Supplies
D Available in a 48-Pin TSSOP Package or
56-Ball MicroStar Junior™ BGA Package
D Consumes < 100-μA Quiescent Current
D External Feedback Pins (FBIN, FBIN) Are
Used to Synchronize the Outputs to the
Input Clocks
D Meets/Exceeds the Latest DDR JEDEC
Spec JESD82−1
Description
The CDCV857B is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock
input pair (CLK, CLK) to 10 differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback
clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback
clocks (FBIN, FBIN), and the analog power input (AVDD). When PWRDWN is high, theoutputs switch in phase
and frequency with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state (3-state)
and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input
frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input
frequency detection circuit detects the low frequency condition and, after applying a >20-MHz input signal, this
detection circuit turns the PLL on and enables the outputs.
When AVDD is strapped low, the PLL is turned off and bypassed for test purposes. The CDCV857B is also able
to track spread spectrum clocking for reduced EMI.
Since the CDCV857B is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.
This stabilization time is required following power up. The CDCV857B is characterized for both commercial and
industrial temperature ranges.
AVAILABLE OPTIONS
TA
TSSOP (DGG)
MicroStar Junior™ BGA (GQL)
0°C to 85°C
CDCV857BDGG
CDCV857BGQL
−40°C to 85°C
CDCV857BIDGG
FUNCTION TABLE
(Select Functions)
INPUTS
OUTPUTS
PLL
AVDD
PWRDWN
CLK
CLK
Y[0:9]
Y[0:9]
FBOUT
FBOUT
GND
H
L
H
L
H
L
H
Bypassed/Off
GND
H
H
L
H
L
H
L
Bypassed/Off
X
L
L
H
Z
Z
Z
Z
Off
X
L
H
L
Z
Z
Z
Z
Off
2.5 V (nom)
H
L
H
L
H
L
H
On
2.5 V (nom)
H
H
L
H
L
H
L
On
2.5 V (nom)
X
<20 MHz
<20 MHz
Z
Z
Z
Z
Off
Copyright © 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MicroStar Junior is a trademark of Texas Instruments Incorporated.


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