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Si1060-A-GM Arkusz danych(PDF) 11 Page - Silicon Laboratories |
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Si1060-A-GM Arkusz danych(HTML) 11 Page - Silicon Laboratories |
11 / 358 page Si106x/108x 11 Rev. 1.0 Table 19.3. SmaRTClock Bias Settings ................................................................ 210 Table 20.1. Port I/O Assignment for Analog Functions ......................................... 220 Table 20.2. Port I/O Assignment for Digital Functions ........................................... 220 Table 20.3. Port I/O Assignment for External Digital Event Capture Functions .... 221 Table 21.1. Internal Connection for Radio and MCU ............................................. 238 Table 21.2. Serial Interface Timing Parameters .................................................... 238 Table 21.3. Operating State Response Time and Current Consumption Si1060/61/62/63, Si1080/81/82/83 ..................................................... 242 Table 21.4. Operating State Response Time and Current Consumption (Si1064/65, Si1084/85) ....................................................................... 242 Table 21.5. POR Timing ........................................................................................ 243 Table 21.6. GPIOs ................................................................................................. 247 Table 23.1. Recommended Preamble Length ....................................................... 251 Table 24.1. Output Divider (Outdiv) Values for the Si1060–Si1063, Si1080-1083 256 Table 24.2. Output Divider (Outdiv) for the Si1064/Si1065/Si1084/Si1085 ........... 256 Table 27.1. WUT Specific Commands and Properties .......................................... 264 Table 28.1. SMBus Clock Source Selection .......................................................... 271 Table 28.2. Minimum SDA Setup and Hold Times ................................................ 272 Table 28.3. Sources for Hardware Changes to SMB0CN ..................................... 276 Table 28.4. Hardware Address Recognition Examples (EHACK = 1) ................... 277 Table 28.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0) ....................................................................................... 286 Table 28.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1) ....................................................................................... 288 Table 29.1. Timer Settings for Standard Baud Rates Using The Internal 24.5 MHz Oscillator .............................................. 297 Table 29.2. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz Oscillator ......................................... 297 Table 30.1. SPI Slave Timing Parameters ............................................................ 310 Table 31.1. Timer 0 Running Modes ..................................................................... 313 Table 32.1. PCA Timebase Input Options ............................................................. 334 Table 32.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules .............................................................................................. 336 Table 32.3. Watchdog Timer Timeout Intervals1 ................................................... 345 |
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