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Si4721-B20-GM Arkusz danych(PDF) 10 Page - Silicon Laboratories |
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Si4721-B20-GM Arkusz danych(HTML) 10 Page - Silicon Laboratories |
10 / 48 page Si4720/21-B20 10 Rev. 1.0 Figure 4. 3-Wire Control Interface Write Timing Parameters Figure 5. 3-Wire Control Interface Read Timing Parameters Table 6. 3-Wire Control Interface Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit SCLK Frequency fCLK 0— 2.5 MHz SCLK High Time tHIGH 25 — — ns SCLK Low Time tLOW 25 — — ns SDIO Input, SEN to SCLK Setup tS 20 — — ns SDIO Input to SCLK Hold tHSDIO 10 — — ns SEN Input to SCLK Hold tHSEN 10 — — ns SCLK to SDIO Output Valid tCDV Read 2 — 25 ns SCLK to SDIO Output High Z tCDZ Read 2 — 25 ns SCLK, SEN, SDIO, Rise/Fall time tR, tF — — 10 ns Note: When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST. SCLK 70% 30% SEN 70% 30% SDIO A7 A0 70% 30% tS tS tHSDIO tHSEN A6-A5, R/W, A4-A1 Address In Data In D15 D14-D1 D0 tHIGH tLOW tR tF ½ Cycle Bus Turnaround SCLK 70% 30% SEN 70% 30% SDIO 70% 30% tHSDIO tCDV tCDZ Address In Data Out A7 A0 A6-A5, R/W, A4-A1 D15 D14-D1 D0 tS tS tHSEN |
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