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TS68EN360MA33L Arkusz danych(PDF) 7 Page - ATMEL Corporation

Numer części TS68EN360MA33L
Szczegółowy opis  32-bitQuad Integrated Communication Controller
Download  82 Pages
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Producent  ATMEL [ATMEL Corporation]
Strona internetowa  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

TS68EN360MA33L Arkusz danych(HTML) 7 Page - ATMEL Corporation

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TS68EN360
2113A–HIREL–03/02
Bus Control
Data and Size
Acknowledge
DSACK1 - DSACK0
Provides asynchronous data transfer acknowledgement and
dynamic bus sizing (open-drain I/O but driven high before
three-stated).
Address Strobe
AS
Indicates that a valid address is on the address bus. (I/O)
Data Strobe
DS
During a read cycle, DS indicates that an external device
should place valid data on the data bus. During a write cycle,
DS indicates that valid data is on the data bus. (I/O)
Size
SIZ1-SIZ0
Indicates the number of bytes remaining to be transferred for
this cycle. (I/O)
Read/Write
R/W
Indicates the direction of data transfer on the bus. (I/O)
Output Enable Address
Multiplex
OE/AMUX
Active during a read cycle indicates that an external device
should place valid data on the data bus (O) or provides a
strobe for external address multiplexing in DRAM accesses
if internal multiplexing is not used. (O)
Interrupt
Control
Interrupt Request
Level 7-1
IRQ7-IRQ1
Provides external interrupt requests to the CPU32+ at
priority levels 7-1. (I)
Autovector/Interrupt
Acknowledge 5
AVEC/IACK5
Autovector request during an interrupt acknowledge cycle
(open-drain I/O) or interrupt level 5 acknowledge line. (O)
System
Control
Soft Reset
RESETS
Soft system reset. (open-drain I/O)
Hard Reset
RESETH
Hard system reset. (open-drain I/O)
Halt
HALT
Suspends external bus activity. (open-drain I/O)
Bus Error
BERR
Indicates an erroneous bus operation is being attempted.
(open-drain I/O)
Clock and Test
System Clock Out 1
CLKO1
Internal system clock output 1. (O)
System Clock Out 2
CLKO2
Internal system clock output 2 - normally 2x CLKO1. (O)
Crystal Oscillator
EXTAL, XTAL
Connections for an external crystal to the internal oscillator
circuit. EXTAL (I), XTAL (O).
External Filter Capacitor
XFC
Connection pin for an external capacitor to filter the circuit of
the PLL. (I)
Clock Mode Select 1-0
MODCK1-MODCK0
Selects the source of the internal system clock. (I) THESE
PINS SHOULD NOT BE SET TO 00
Instruction Fetch/
Development Serial Input
IFETCH/DSI
Indicates when the CPU32+ is performing an instruction
word prefetch (O) or input to the CPU32+ background debug
mode. (I)
Instruction Pipe 0/
Development Serial
Output
IPIPE0/DSO
Used to track movement of words through the instruction
pipeline (O) or output from the CPU32+ background debug
mode. (O)
Instruction Pipe 1/Row
Address Select 1
Double-Drive
IPIPE1/RAS1DD
Used to track movement of words through the instruction
pipeline (O), or a row address select 1 “double-drive” output
(O).
Breakpoint/Development
Serial Clock
BKPT/DSCLK
Signals a hardware breakpoint to the QUICC (open-drain
I/O), or clock signal for CPU32+ background debug mode (I).
Freeze/Initial
Configuration 2
FREEZE/CONFIG2
Indicates that the CPU32+ has acknowledged a breakpoint
(O), or initial QUICC configuration select (I).
Table 1. System Bus Signal Index (Normal Operation) (Continued)
Group
Signal Name
Mnemonic
Function


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