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TP11362AV Arkusz danych(PDF) 10 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Numer części TP11362AV
Szczegółowy opis  Quad Adaptive Differential PCM Processor
Download  16 Pages
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Producent  NSC [National Semiconductor (TI)]
Strona internetowa  http://www.national.com
Logo NSC - National Semiconductor (TI)

TP11362AV Arkusz danych(HTML) 10 Page - National Semiconductor (TI)

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Absolute Maximum Ratings (Note *NO
TGT: FNXref NS0465*)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V
CC to GND
7V
Voltage at Any Digital
Inputs or Outputs
GND − 0.3V to V
CC + 0.3V
Storage Temperature Range
−45˚C to +125˚C
Lead Temperature
(Soldering, 10 sec)
300˚C
Latch-up Immunity on any Pin
±75 mA
θ
JA (28-pin PLCC)
79˚C/W
θ
JA (24-pin DIP)
49˚C/W
DC Electrical Characteristics
Unless otherwise noted, limits printed in bold characters are guaranteed forV
CC = 5.0V ± 5%, GND1 = GND2 = 0V, TA =
−40˚C to +85˚C by correlation with 100% electrical testing at T
A = 25˚C. All other limits are assured by correlation with other
production tests and/or product design and characterization. Typical values are specified at V
CC = +5V, TA = 25˚C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
I
CC0
Supply Current
CLK = 8.0 MHz, RSTB = Low
1.8
mA
(Power Down Mode)
I
CC1
Supply Current
CLK = 8.0 MHz, RSTB = High
7
9
mA
(Power Up Mode)
P
D
Power Dissipation
35
mW
V
IL
Input Low Voltage
ASCK, PSCK, CE, TRB,
0.8
V
V
IH
Input High Voltage
CLK, RSTB
2.4
V
V
IL
Input Low Voltage
PCM1, RSI, TSI, QSEL0,
0.7
V
V
IH
Input High Voltage
QSEL1, INIT, EN
2.0
V
V
OL
Output Low Voltage
I
L = 4mA
0.4
V
V
OH
Output High Voltage
I
L = −4 mA
2.4
V
I
L = −0.4 mA; VCC = 4.75V
V
CC − 0.8
V
I
IL
Input Low Current
GND < V
IN < VIL, All Signal Inputs
−10
µA
I
IH
Input High Current
V
IH < VIN < VCC, All Signal Inputs
10
µA
Test Inputs TST0, TST1, TST2 (Note 4)
150
µA
I
OZ
Output Current in High
GND < V
O < VCC, TSO and RS0
−10
10
µA
Impedance State
C
I
Input Capacitance
10
pF
C
O
Output Capacitance
10
pF
C
L
Capacitive Load
100
pF
Note 4: Test inputs have internal pull-down resistor.
Timing Specifications
Unless otherwise noted, limits printed in bold characters are guaranteed for V
CC = 5.0V ± 5%, GND1 = GND2 = 0V, TA =
−40˚C to +85˚C by correlation with 100% electrical testing at T
A = 25˚C. All other limits are assured by correlation with other
production tests and/or product design and characterization. Typical values are specified at V
CC = +5V, TA = 25˚C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
f
CLK
CLK Frequency (Note 5)
Assuming 50% Duty Cycle
7.9
8.0
16
MHz
t
CLK
CLK Duty-Cycle
40%
50%
60%
CLK
Period
t
R
Rise Time (CLK, CE,
10
ns
ASCK, PSCK)
t
F
Fall Time (CLK, CE,
10
ns
ASCK, PSCK)
t
CEP
CE Period
Encode or Decode
123
CLK
Initialization
45
Cycles
Disable
9
t
CEL
CE Pulse Width, Low
4
CLK
Cycles
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